linux/drivers/pci/controller/mobiveil/pcie-mobiveil.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCIe host controller driver for Mobiveil PCIe Host controller
 *
 * Copyright (c) 2018 Mobiveil Inc.
 * Copyright 2019 NXP
 *
 * Author: Subrahmanya Lingappa <[email protected]>
 *	   Hou Zhiqiang <[email protected]>
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

#include "pcie-mobiveil.h"

/*
 * mobiveil_pcie_sel_page - routine to access paged register
 *
 * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
 * for this scheme to work extracted higher 6 bits of the offset will be
 * written to pg_sel field of PAB_CTRL register and rest of the lower 10
 * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
 */
static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
{ … }

static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie,
					     u32 off)
{ … }

static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
{ … }

static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
{ … }

u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
{ … }

void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
			       size_t size)
{ … }

bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
{ … }

void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
			u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
{ … }

/*
 * routine to program the outbound windows
 */
void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
			u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
{ … }

int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
{ … }