/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for the new Marvell Yukon / SysKonnect driver. */ #ifndef _SKGE_H #define _SKGE_H #include <linux/interrupt.h> /* PCI config registers */ #define PCI_DEV_REG1 … #define PCI_PHY_COMA … #define PCI_VIO … #define PCI_DEV_REG2 … #define PCI_VPD_ROM_SZ … #define PCI_REV_DESC … enum csr_regs { … }; /* B0_CTST 16 bit Control/Status register */ enum { … }; /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ enum { … }; /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ enum { … }; /* B2_TST_CTRL1 8 bit Test Control Register 1 */ enum { … }; /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ enum { … }; /* B2_CHIP_ID 8 bit Chip Identification Number */ enum { … }; /* B2_TI_CTRL 8 bit Timer control */ /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ enum { … }; /* B2_TI_TEST 8 Bit Timer Test */ /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ enum { … }; /* B2_GP_IO 32 bit General Purpose I/O Register */ enum { … }; /* Descriptor Bit Definition */ /* TxCtrl Transmit Buffer Control Field */ /* RxCtrl Receive Buffer Control Field */ enum { … }; /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ enum { … }; /* B2_BSC_STAT 8 bit Blink Source Counter Status */ enum { … }; /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ enum { … }; /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ /* Bit 31..19: reserved */ #define RAM_ADR_RAN … /* RAM Interface Registers */ /* B3_RI_CTRL 16 bit RAM Iface Control Register */ enum { … }; /* MAC Arbiter Registers */ /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ enum { … }; /* Timeout values */ #define SK_MAC_TO_53 … #define SK_PKT_TO_53 … #define SK_PKT_TO_MAX … #define SK_RI_TO_53 … /* Packet Arbiter Registers */ /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ enum { … }; #define PA_ENA_TO_ALL … /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ #define TXA_MAX_VAL … /* TXA_CTRL 8 bit Tx Arbiter Control Register */ enum { … }; /* * Bank 4 - 5 */ /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ enum { … }; enum { … }; /* Queue Register Offsets, use Q_ADDR() to access */ enum { … }; #define Q_ADDR(reg, offs) … /* RAM Buffer Register Offsets */ enum { … }; /* Receive and Transmit Queues */ enum { … }; /* Different MAC Types */ enum { … }; /* Different PHY Types */ enum { … }; /* PHY addresses (bits 12..8 of PHY address reg) */ enum { … }; #define RB_ADDR(offs, queue) … /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */ enum { … }; /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */ enum { … }; /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ enum { … }; /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ enum { … }; /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ enum { … }; /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ enum { … }; /* Link LED Counter Registers (GENESIS only) */ /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ enum { … }; /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ enum { … }; /* LNK_LED_REG 8 bit Link LED Register */ enum { … }; /* Receive GMAC FIFO (YUKON) */ enum { … }; /* TXA_TEST 8 bit Tx Arbiter Test Register */ enum { … }; /* TXA_STAT 8 bit Tx Arbiter Status Register */ enum { … }; /* Q_BC 32 bit Current Byte Counter */ /* BMU Control Status Registers */ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ /* Q_CSR 32 bit BMU Control/Status Register */ enum { … }; #define CSR_SET_RESET … #define CSR_CLR_RESET … /* Q_F 32 bit Flag Register */ enum { … }; /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ /* RB_START 32 bit RAM Buffer Start Address */ /* RB_END 32 bit RAM Buffer End Address */ /* RB_WP 32 bit RAM Buffer Write Pointer */ /* RB_RP 32 bit RAM Buffer Read Pointer */ /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ /* RB_PC 32 bit RAM Buffer Packet Counter */ /* RB_LEV 32 bit RAM Buffer Level Register */ #define RB_MSK … /* RB_TST2 8 bit RAM Buffer Test Register 2 */ /* RB_TST1 8 bit RAM Buffer Test Register 1 */ /* RB_CTRL 8 bit RAM Buffer Control Register */ enum { … }; /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */ enum { … }; /* Counter and Timer constants, for a host clock of 62.5 MHz */ #define SK_XMIT_DUR … #define SK_BLK_DUR … #define SK_DPOLL_DEF … #define SK_DPOLL_MAX … /* 215 ms at 78.12 MHz */ #define SK_FACT_62 … #define SK_FACT_53 … #define SK_FACT_78 … /* Transmit GMAC FIFO (YUKON only) */ enum { … }; enum { … }; /* GMAC and GPHY Control Registers (YUKON only) */ enum { … }; #define WOL_REGS(port, x) … enum { … }; #define WOL_PATT_RAM_BASE(port) … enum { … }; /* * Receive Frame Status Encoding */ enum { … }; /* ,* XMAC-PHY Registers, indirect addressed over the XMAC */ enum { … }; /* * Broadcom-PHY Registers, indirect addressed over XMAC */ enum { … }; /* * Marvel-PHY Registers, indirect addressed over GMAC */ enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; /* different Broadcom PHY Ids */ enum { … }; /* different Marvell PHY Ids */ enum { … }; /* Advertisement register bits */ enum { … }; /* Xmac Specific */ enum { … }; /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ enum { … }; /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ enum { … }; /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ enum { … }; /* Remote Fault Bits (PHY_X_AN_RFB) encoding */ enum { … }; /* Broadcom-Specific */ /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ enum { … }; /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ enum { … }; /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ enum { … }; /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ enum { … }; /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ enum { … }; /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ enum { … }; /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ enum { … }; /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ enum { … }; #define PHY_B_AS_PAUSE_MSK … /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ enum { … }; #define PHY_B_DEF_MSK … /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ enum { … }; /* * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) */ enum { … }; /** Marvell-Specific */ enum { … }; /* special defines for FIBER (88E1011S only) */ enum { … }; /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ enum { … }; /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ enum { … }; /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ enum { … }; enum { … }; enum { … }; /* for 10/100 Fast Ethernet PHY (88E3082 only) */ enum { … }; /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ enum { … }; #define PHY_M_PS_PAUSE_MSK … /* for 10/100 Fast Ethernet PHY (88E3082 only) */ enum { … }; enum { … }; /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ enum { … }; #define PHY_M_EC_M_DSC(x) … #define PHY_M_EC_S_DSC(x) … #define PHY_M_EC_MAC_S(x) … #define PHY_M_EC_M_DSC_2(x) … /* 100=5x; 101=6x; 110=7x; 111=8x */ enum { … }; /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ enum { … }; #define PHY_M_LED_PULS_DUR(x) … #define PHY_M_LED_BLINK_RT(x) … enum { … }; enum { … }; enum { … }; /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ #define PHY_M_LED_MO_SGMII(x) … /* Bit 13..12: reserved */ #define PHY_M_LED_MO_DUP(x) … #define PHY_M_LED_MO_10(x) … #define PHY_M_LED_MO_100(x) … #define PHY_M_LED_MO_1000(x) … #define PHY_M_LED_MO_RX(x) … #define PHY_M_LED_MO_TX(x) … enum { … }; /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ enum { … }; /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ enum { … }; /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ enum { … }; /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ enum { … }; /* for 10/100 Fast Ethernet PHY (88E3082 only) */ /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ /* Bit 15..12: reserved (used internally) */ enum { … }; #define PHY_M_FELP_LED2_CTRL(x) … #define PHY_M_FELP_LED1_CTRL(x) … #define PHY_M_FELP_LED0_CTRL(x) … enum { … }; /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ enum { … }; /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ enum { … }; #define PHY_M_LEDC_LOS_CTRL(x) … #define PHY_M_LEDC_INIT_CTRL(x) … #define PHY_M_LEDC_STA1_CTRL(x) … #define PHY_M_LEDC_STA0_CTRL(x) … /* GMAC registers */ /* Port Registers */ enum { … }; /* MIB Counters */ #define GM_MIB_CNT_BASE … #define GM_MIB_CNT_SIZE … /* * MIB Counters base address definitions (low word) - * use offset 4 for access to high word (32 bit r/o) */ enum { … }; /* GMAC Bit Definitions */ /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ enum { … }; /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ enum { … }; #define GM_GPCR_SPEED_1000 … #define GM_GPCR_AU_ALL_DIS … /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ enum { … }; #define TX_COL_THR(x) … #define TX_COL_DEF … /* GM_RX_CTRL 16 bit r/w Receive Control Register */ enum { … }; /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ enum { … }; #define TX_JAM_LEN_VAL(x) … #define TX_JAM_IPG_VAL(x) … #define TX_IPG_JAM_DATA(x) … /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ enum { … }; #define DATA_BLIND_VAL(x) … #define DATA_BLIND_DEF … #define IPG_DATA_VAL(x) … #define IPG_DATA_DEF … /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ enum { … }; #define GM_SMI_CT_PHY_AD(x) … #define GM_SMI_CT_REG_AD(x) … /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ enum { … }; /* Receive Frame Status Encoding */ enum { … }; /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ enum { … }; /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ enum { … }; /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ enum { … }; /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ enum { … }; /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ enum { … }; #define GPC_HWCFG_GMII_COP … #define GPC_HWCFG_GMII_FIB … #define GPC_ANEG_ADV_ALL_M … /* forced speed and duplex mode (don't mix with other ANEG bits) */ #define GPC_FRC10MBIT_HALF … #define GPC_FRC10MBIT_FULL … #define GPC_FRC100MBIT_HALF … #define GPC_FRC100MBIT_FULL … /* auto-negotiation with limited advertised speeds */ /* mix only with master/slave settings (for copper) */ #define GPC_ADV_1000_HALF … #define GPC_ADV_1000_FULL … #define GPC_ADV_ALL … /* master/slave settings */ /* only for copper with 1000 Mbps */ #define GPC_FORCE_MASTER … #define GPC_FORCE_SLAVE … #define GPC_PREF_MASTER … #define GPC_PREF_SLAVE … /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ enum { … }; #define WOL_CTL_DEFAULT … /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ #define WOL_CTL_PATT_ENA(x) … /* XMAC II registers */ enum { … }; enum { … }; /* XM_MMU_CMD 16 bit r/w MMU Command Register */ enum { … }; /* XM_TX_CMD 16 bit r/w Transmit Command Register */ enum { … }; /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ #define XM_RT_LIM_MSK … /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ #define XM_STIME_MSK … /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ #define XM_IPG_MSK … /* XM_RX_CMD 16 bit r/w Receive Command Register */ enum { … }; /* XM_GP_PORT 32 bit r/w General Purpose Port Register */ enum { … }; /* XM_IMSK 16 bit r/w Interrupt Mask Register */ /* XM_ISRC 16 bit r/o Interrupt Status Register */ enum { … }; /* XM_HW_CFG 16 bit r/w Hardware Config Register */ enum { … }; /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ #define XM_TX_WM_MSK … /* XM_TX_THR 16 bit r/w Tx Request Threshold */ /* XM_HT_THR 16 bit r/w Host Request Threshold */ /* XM_RX_THR 16 bit r/w Rx Request Threshold */ #define XM_THR_MSK … /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */ enum { … }; /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ #define XM_RX_WM_MSK … /* XM_DEV_ID 32 bit r/o Device ID Register */ #define XM_DEV_OUI … #define XM_DEV_REV … /* XM_MODE 32 bit r/w Mode Register */ enum { … }; #define XM_PAUSE_MODE … #define XM_DEF_MODE … /* XM_STAT_CMD 16 bit r/w Statistics Command Register */ enum { … }; /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ enum { … }; #define XMR_DEF_MSK … /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ enum { … }; #define XMT_DEF_MSK … struct skge_rx_desc { … }; struct skge_tx_desc { … }; struct skge_element { … }; struct skge_ring { … }; struct skge_hw { … }; enum pause_control { … }; enum pause_status { … }; struct skge_port { … }; /* Register accessor for memory mapped device */ static inline u32 skge_read32(const struct skge_hw *hw, int reg) { … } static inline u16 skge_read16(const struct skge_hw *hw, int reg) { … } static inline u8 skge_read8(const struct skge_hw *hw, int reg) { … } static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val) { … } static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val) { … } static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val) { … } /* MAC Related Registers inside the device. */ #define SK_REG(port,reg) … #define SK_XMAC_REG(port, reg) … static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg) { … } static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg) { … } static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v) { … } static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v) { … } static inline void xm_outhash(const struct skge_hw *hw, int port, int reg, const u8 *hash) { … } static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg, const u8 *addr) { … } #define SK_GMAC_REG(port,reg) … static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg) { … } static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg) { … } static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v) { … } static inline void gma_set_addr(struct skge_hw *hw, int port, int reg, const u8 *addr) { … } #endif
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