/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for the new Marvell Yukon 2 driver. */ #ifndef _SKY2_H #define _SKY2_H #define ETH_JUMBO_MTU … /* PCI config registers */ enum { … }; /* Yukon-2 */ enum pci_dev_reg_1 { … }; enum pci_dev_reg_2 { … }; /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ enum pci_dev_reg_3 { … }; /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ enum pci_dev_reg_4 { … }; /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ enum pci_dev_reg_5 { … }; /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */ enum pci_cfg_reg1 { … }; /* Yukon-Optima */ enum { … }; /* Yukon-Supreme */ enum { … }; /* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */ enum { … }; enum csr_regs { … }; /* B0_CTST 24 bit Control/Status register */ enum { … }; /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ enum { … }; /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ enum { … }; /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ enum { … }; /* Hardware error interrupt mask for Yukon 2 */ enum { … }; /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ enum { … }; /* B2_TST_CTRL1 8 bit Test Control Register 1 */ enum { … }; /* B2_GPIO */ enum { … }; /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ enum { … }; /* B2_CHIP_ID 8 bit Chip Identification Number */ enum { … }; enum yukon_xl_rev { … }; enum yukon_ec_rev { … }; enum yukon_ec_u_rev { … }; enum yukon_fe_rev { … }; enum yukon_fe_p_rev { … }; enum yukon_ex_rev { … }; enum yukon_supr_rev { … }; enum yukon_prm_rev { … }; /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ enum { … }; /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ enum { … }; #define CFG_LED_MODE(x) … #define CFG_DUAL_MAC_MSK … /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ enum { … }; /* B2_TI_CTRL 8 bit Timer control */ /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ enum { … }; /* B2_TI_TEST 8 Bit Timer Test */ /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ enum { … }; /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ enum { … }; /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ /* Bit 31..19: reserved */ #define RAM_ADR_RAN … /* RAM Interface Registers */ /* B3_RI_CTRL 16 bit RAM Interface Control Register */ enum { … }; #define SK_RI_TO_53 … /* Port related registers FIFO, and Arbiter */ #define SK_REG(port,reg) … /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ #define TXA_MAX_VAL … /* TXA_CTRL 8 bit Tx Arbiter Control Register */ enum { … }; /* * Bank 4 - 5 */ /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ enum { … }; enum { … }; enum { … }; /* Queue Register Offsets, use Q_ADDR() to access */ enum { … }; #define Q_ADDR(reg, offs) … /* Q_TEST 32 bit Test Register */ enum { … }; /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ enum { … }; #define Y2_QADDR(q,reg) … /* RAM Buffer Register Offsets */ enum { … }; /* Receive and Transmit Queues */ enum { … }; /* Different PHY Types */ enum { … }; #define RB_ADDR(offs, queue) … enum { … }; /* Q_BC 32 bit Current Byte Counter */ /* BMU Control Status Registers */ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ /* Q_CSR 32 bit BMU Control/Status Register */ /* Rx BMU Control / Status Registers (Yukon-2) */ enum { … }; /* Tx BMU Control / Status Registers (Yukon-2) */ /* Bit 31: same as for Rx */ enum { … }; /* TBMU_TEST 0x06B8 Transmit BMU Test Register */ enum { … }; /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ enum { … }; /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ /* RB_START 32 bit RAM Buffer Start Address */ /* RB_END 32 bit RAM Buffer End Address */ /* RB_WP 32 bit RAM Buffer Write Pointer */ /* RB_RP 32 bit RAM Buffer Read Pointer */ /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ /* RB_PC 32 bit RAM Buffer Packet Counter */ /* RB_LEV 32 bit RAM Buffer Level Register */ #define RB_MSK … /* RB_TST2 8 bit RAM Buffer Test Register 2 */ /* RB_TST1 8 bit RAM Buffer Test Register 1 */ /* RB_CTRL 8 bit RAM Buffer Control Register */ enum { … }; /* Transmit GMAC FIFO (YUKON only) */ enum { … }; /* Descriptor Poll Timer Registers */ enum { … }; /* Time Stamp Timer Registers (YUKON only) */ enum { … }; /* Polling Unit Registers (Yukon-2 only) */ enum { … }; enum { … }; enum { … }; /* ASF Subsystem Registers (Yukon-2 only) */ enum { … }; /* Status BMU Registers (Yukon-2 only)*/ enum { … }; enum { … }; /* GMAC and GPHY Control Registers (YUKON only) */ enum { … }; #define WOL_REGS(port, x) … enum { … }; #define WOL_PATT_RAM_BASE(port) … enum { … }; /* * Marvel-PHY Registers, indirect addressed over GMAC */ enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; /* different Marvell PHY Ids */ enum { … }; /* Advertisement register bits */ enum { … }; /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ enum { … }; /** Marvell-Specific */ enum { … }; /* special defines for FIBER (88E1011S only) */ enum { … }; /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ enum { … }; /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ enum { … }; /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ enum { … }; enum { … }; #define PHY_M_PC_MDI_XMODE(x) … enum { … }; /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */ enum { … }; /* for 10/100 Fast Ethernet PHY (88E3082 only) */ enum { … }; /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ enum { … }; #define PHY_M_PS_PAUSE_MSK … /* for 10/100 Fast Ethernet PHY (88E3082 only) */ enum { … }; enum { … }; /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ enum { … }; #define PHY_M_EC_M_DSC(x) … /* 00=1x; 01=2x; 10=3x; 11=4x */ #define PHY_M_EC_S_DSC(x) … /* 00=dis; 01=1x; 10=2x; 11=3x */ #define PHY_M_EC_DSC_2(x) … /* 000=1x; 001=2x; 010=3x; 011=4x */ #define PHY_M_EC_MAC_S(x) … /* 01X=0; 110=2.5; 111=25 (MHz) */ /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ enum { … }; /* !!! Errata in spec. (1 = disable) */ #define PHY_M_PC_DSC(x) … /* 100=5x; 101=6x; 110=7x; 111=8x */ enum { … }; /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ enum { … }; enum { … }; #define PHY_M_LED_PULS_DUR(x) … /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ enum { … }; #define PHY_M_POLC_LS1_P_MIX(x) … #define PHY_M_POLC_IS0_P_MIX(x) … #define PHY_M_POLC_LOS_CTRL(x) … #define PHY_M_POLC_INIT_CTRL(x) … #define PHY_M_POLC_STA1_CTRL(x) … #define PHY_M_POLC_STA0_CTRL(x) … enum { … }; #define PHY_M_LED_BLINK_RT(x) … enum { … }; /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ #define PHY_M_LED_MO_SGMII(x) … #define PHY_M_LED_MO_DUP(x) … #define PHY_M_LED_MO_10(x) … #define PHY_M_LED_MO_100(x) … #define PHY_M_LED_MO_1000(x) … #define PHY_M_LED_MO_RX(x) … #define PHY_M_LED_MO_TX(x) … enum led_mode { … }; /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ enum { … }; /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ enum { … }; /* for 10/100 Fast Ethernet PHY (88E3082 only) */ /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ /* Bit 15..12: reserved (used internally) */ enum { … }; #define PHY_M_FELP_LED2_CTRL(x) … #define PHY_M_FELP_LED1_CTRL(x) … #define PHY_M_FELP_LED0_CTRL(x) … enum { … }; /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ enum { … }; /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ enum { … }; /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ enum { … }; #define PHY_M_MAC_MODE_SEL(x) … /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ enum { … }; #define PHY_M_LEDC_LOS_CTRL(x) … #define PHY_M_LEDC_INIT_CTRL(x) … #define PHY_M_LEDC_STA1_CTRL(x) … #define PHY_M_LEDC_STA0_CTRL(x) … /* GMAC registers */ /* Port Registers */ enum { … }; /* * MIB Counters base address definitions (low word) - * use offset 4 for access to high word (32 bit r/o) */ enum { … }; /* GMAC Bit Definitions */ /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ enum { … }; /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ enum { … }; #define GM_GPCR_SPEED_1000 … /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ enum { … }; #define TX_COL_THR(x) … #define TX_COL_DEF … /* GM_RX_CTRL 16 bit r/w Receive Control Register */ enum { … }; /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ enum { … }; #define TX_JAM_LEN_VAL(x) … #define TX_JAM_IPG_VAL(x) … #define TX_IPG_JAM_DATA(x) … #define TX_BACK_OFF_LIM(x) … /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ enum { … }; #define DATA_BLIND_VAL(x) … #define IPG_DATA_VAL(x) … #define DATA_BLIND_DEF … #define IPG_DATA_DEF_1000 … #define IPG_DATA_DEF_10_100 … /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ enum { … }; #define GM_SMI_CT_PHY_AD(x) … #define GM_SMI_CT_REG_AD(x) … /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ enum { … }; /* Receive Frame Status Encoding */ enum { … }; /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ enum { … }; /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */ enum { … }; /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ enum { … }; /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ enum { … }; /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ enum { … }; /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ enum { … }; /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ enum { … }; /* HCU_CCSR CPU Control and Status Register */ enum { … }; /* HCU_HCSR Host Control and Status Register */ enum { … }; /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ enum { … }; /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ enum { … }; /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ enum { … }; /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ enum { … }; /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ enum { … }; /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ enum { … }; /* Control flags */ enum { … }; enum { … }; enum status_css { … }; /* Yukon 2 hardware interface */ struct sky2_tx_le { … } __packed; struct sky2_rx_le { … } __packed; struct sky2_status_le { … } __packed; struct tx_ring_info { … }; struct rx_ring_info { … }; enum flow_control { … }; struct sky2_stats { … }; struct sky2_port { … }; struct sky2_hw { … }; static inline int sky2_is_copper(const struct sky2_hw *hw) { … } /* Register accessor for memory mapped device */ static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) { … } static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) { … } static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) { … } static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) { … } static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) { … } static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) { … } /* Yukon PHY related registers */ #define SK_GMAC_REG(port,reg) … #define GM_PHY_RETRIES … static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) { … } static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) { … } static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg) { … } /* There is no way to atomically read32 bit values from PHY, so retry */ static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg) { … } static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg) { … } static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) { … } static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, const u8 *addr) { … } /* PCI config space access */ static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) { … } static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) { … } static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) { … } static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) { … } #endif
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