/* SPDX-License-Identifier: GPL-2.0-only */ /* * * Copyright (C) 2009-2016 John Crispin <[email protected]> * Copyright (C) 2009-2016 Felix Fietkau <[email protected]> * Copyright (C) 2013-2016 Michael Lee <[email protected]> */ #ifndef MTK_ETH_H #define MTK_ETH_H #include <linux/dma-mapping.h> #include <linux/netdevice.h> #include <linux/of_net.h> #include <linux/u64_stats_sync.h> #include <linux/refcount.h> #include <linux/phylink.h> #include <linux/rhashtable.h> #include <linux/dim.h> #include <linux/bitfield.h> #include <net/page_pool/types.h> #include <linux/bpf_trace.h> #include "mtk_ppe.h" #define MTK_MAX_DSA_PORTS … #define MTK_DSA_PORT_MASK … #define MTK_QDMA_NUM_QUEUES … #define MTK_QDMA_PAGE_SIZE … #define MTK_MAX_RX_LENGTH … #define MTK_MAX_RX_LENGTH_2K … #define MTK_TX_DMA_BUF_LEN … #define MTK_TX_DMA_BUF_LEN_V2 … #define MTK_QDMA_RING_SIZE … #define MTK_DMA_SIZE(x) … #define MTK_FQ_DMA_HEAD … #define MTK_FQ_DMA_LENGTH … #define MTK_RX_ETH_HLEN … #define MTK_RX_HLEN … #define MTK_DMA_DUMMY_DESC … #define MTK_DEFAULT_MSG_ENABLE … #define MTK_HW_FEATURES … #define MTK_HW_FEATURES_MT7628 … #define NEXT_DESP_IDX(X, Y) … #define MTK_PP_HEADROOM … #define MTK_PP_PAD … #define MTK_PP_MAX_BUF_SIZE … #define MTK_QRX_OFFSET … #define MTK_MAX_RX_RING_NUM … #define MTK_HW_LRO_DMA_SIZE … #define MTK_MAX_LRO_RX_LENGTH … #define MTK_MAX_LRO_IP_CNT … #define MTK_HW_LRO_TIMER_UNIT … #define MTK_HW_LRO_REFRESH_TIME … #define MTK_HW_LRO_AGG_TIME … #define MTK_HW_LRO_AGE_TIME … #define MTK_HW_LRO_MAX_AGG_CNT … #define MTK_HW_LRO_BW_THRE … #define MTK_HW_LRO_REPLACE_DELTA … #define MTK_HW_LRO_SDL_REMAIN_ROOM … /* Frame Engine Global Configuration */ #define MTK_FE_GLO_CFG(x) … #define MTK_FE_LINK_DOWN_P(x) … /* Frame Engine Global Reset Register */ #define MTK_RST_GL … #define RST_GL_PSE … /* Frame Engine Interrupt Status Register */ #define MTK_INT_STATUS2 … #define MTK_FE_INT_ENABLE … #define MTK_FE_INT_FQ_EMPTY … #define MTK_FE_INT_TSO_FAIL … #define MTK_FE_INT_TSO_ILLEGAL … #define MTK_FE_INT_TSO_ALIGN … #define MTK_FE_INT_RFIFO_OV … #define MTK_FE_INT_RFIFO_UF … #define MTK_GDM1_AF … #define MTK_GDM2_AF … /* PDMA HW LRO Alter Flow Timer Register */ #define MTK_PDMA_LRO_ALT_REFRESH_TIMER … /* Frame Engine Interrupt Grouping Register */ #define MTK_FE_INT_GRP … /* CDMP Ingress Control Register */ #define MTK_CDMQ_IG_CTRL … #define MTK_CDMQ_STAG_EN … /* CDMQ Exgress Control Register */ #define MTK_CDMQ_EG_CTRL … /* CDMP Ingress Control Register */ #define MTK_CDMP_IG_CTRL … #define MTK_CDMP_STAG_EN … /* CDMP Exgress Control Register */ #define MTK_CDMP_EG_CTRL … /* GDM Exgress Control Register */ #define MTK_GDMA_FWD_CFG(x) … #define MTK_GDMA_SPECIAL_TAG … #define MTK_GDMA_ICS_EN … #define MTK_GDMA_TCS_EN … #define MTK_GDMA_UCS_EN … #define MTK_GDMA_STRP_CRC … #define MTK_GDMA_TO_PDMA … #define MTK_GDMA_DROP_ALL … /* GDM Egress Control Register */ #define MTK_GDMA_EG_CTRL(x) … #define MTK_GDMA_XGDM_SEL … /* Unicast Filter MAC Address Register - Low */ #define MTK_GDMA_MAC_ADRL(x) … /* Unicast Filter MAC Address Register - High */ #define MTK_GDMA_MAC_ADRH(x) … /* Internal SRAM offset */ #define MTK_ETH_SRAM_OFFSET … /* FE global misc reg*/ #define MTK_FE_GLO_MISC … /* PSE Free Queue Flow Control */ #define PSE_FQFC_CFG1 … #define PSE_FQFC_CFG2 … #define PSE_DROP_CFG … #define PSE_PPE0_DROP … /* PSE Input Queue Reservation Register*/ #define PSE_IQ_REV(x) … /* PSE Output Queue Threshold Register*/ #define PSE_OQ_TH(x) … /* GDM and CDM Threshold */ #define MTK_GDM2_THRES … #define MTK_CDMW0_THRES … #define MTK_CDMW1_THRES … #define MTK_CDME0_THRES … #define MTK_CDME1_THRES … #define MTK_CDMM_THRES … /* PDMA HW LRO Control Registers */ #define MTK_PDMA_LRO_CTRL_DW0 … #define MTK_LRO_EN … #define MTK_L3_CKS_UPD_EN … #define MTK_L3_CKS_UPD_EN_V2 … #define MTK_LRO_ALT_PKT_CNT_MODE … #define MTK_LRO_RING_RELINQUISH_REQ … #define MTK_LRO_RING_RELINQUISH_REQ_V2 … #define MTK_LRO_RING_RELINQUISH_DONE … #define MTK_LRO_RING_RELINQUISH_DONE_V2 … #define MTK_PDMA_LRO_CTRL_DW1 … #define MTK_PDMA_LRO_CTRL_DW2 … #define MTK_PDMA_LRO_CTRL_DW3 … #define MTK_ADMA_MODE … #define MTK_LRO_MIN_RXD_SDL … #define MTK_RX_DMA_LRO_EN … #define MTK_MULTI_EN … #define MTK_PDMA_SIZE_8DWORDS … /* PDMA Global Configuration Register */ #define MTK_PDMA_LRO_SDL … #define MTK_RX_CFG_SDL_OFFSET … /* PDMA Reset Index Register */ #define MTK_PST_DRX_IDX0 … #define MTK_PST_DRX_IDX_CFG(x) … /* PDMA Delay Interrupt Register */ #define MTK_PDMA_DELAY_RX_MASK … #define MTK_PDMA_DELAY_RX_EN … #define MTK_PDMA_DELAY_RX_PINT_SHIFT … #define MTK_PDMA_DELAY_RX_PTIME_SHIFT … #define MTK_PDMA_DELAY_TX_MASK … #define MTK_PDMA_DELAY_TX_EN … #define MTK_PDMA_DELAY_TX_PINT_SHIFT … #define MTK_PDMA_DELAY_TX_PTIME_SHIFT … #define MTK_PDMA_DELAY_PINT_MASK … #define MTK_PDMA_DELAY_PTIME_MASK … /* PDMA HW LRO Alter Flow Delta Register */ #define MTK_PDMA_LRO_ALT_SCORE_DELTA … /* PDMA HW LRO IP Setting Registers */ #define MTK_LRO_RX_RING0_DIP_DW0 … #define MTK_LRO_DIP_DW0_CFG(x) … #define MTK_RING_MYIP_VLD … /* PDMA HW LRO Ring Control Registers */ #define MTK_LRO_RX_RING0_CTRL_DW1 … #define MTK_LRO_RX_RING0_CTRL_DW2 … #define MTK_LRO_RX_RING0_CTRL_DW3 … #define MTK_LRO_CTRL_DW1_CFG(x) … #define MTK_LRO_CTRL_DW2_CFG(x) … #define MTK_LRO_CTRL_DW3_CFG(x) … #define MTK_RING_AGE_TIME_L … #define MTK_RING_AGE_TIME_H … #define MTK_RING_AUTO_LERAN_MODE … #define MTK_RING_VLD … #define MTK_RING_MAX_AGG_TIME … #define MTK_RING_MAX_AGG_CNT_L … #define MTK_RING_MAX_AGG_CNT_H … /* QDMA TX Queue Configuration Registers */ #define MTK_QTX_OFFSET … #define QDMA_RES_THRES … /* QDMA Tx Queue Scheduler Configuration Registers */ #define MTK_QTX_SCH_TX_SEL … #define MTK_QTX_SCH_TX_SEL_V2 … #define MTK_QTX_SCH_LEAKY_BUCKET_EN … #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE … #define MTK_QTX_SCH_MIN_RATE_EN … #define MTK_QTX_SCH_MIN_RATE_MAN … #define MTK_QTX_SCH_MIN_RATE_EXP … #define MTK_QTX_SCH_MAX_RATE_WEIGHT … #define MTK_QTX_SCH_MAX_RATE_EN … #define MTK_QTX_SCH_MAX_RATE_MAN … #define MTK_QTX_SCH_MAX_RATE_EXP … /* QDMA TX Scheduler Rate Control Register */ #define MTK_QDMA_TX_SCH_MAX_WFQ … /* QDMA Global Configuration Register */ #define MTK_RX_2B_OFFSET … #define MTK_RX_BT_32DWORDS … #define MTK_NDP_CO_PRO … #define MTK_TX_WB_DDONE … #define MTK_TX_BT_32DWORDS … #define MTK_RX_DMA_BUSY … #define MTK_TX_DMA_BUSY … #define MTK_RX_DMA_EN … #define MTK_TX_DMA_EN … #define MTK_DMA_BUSY_TIMEOUT_US … /* QDMA V2 Global Configuration Register */ #define MTK_CHK_DDONE_EN … #define MTK_DMAD_WR_WDONE … #define MTK_WCOMP_EN … #define MTK_RESV_BUF … #define MTK_MUTLI_CNT … #define MTK_LEAKY_BUCKET_EN … /* QDMA Flow Control Register */ #define FC_THRES_DROP_MODE … #define FC_THRES_DROP_EN … #define FC_THRES_MIN … /* QDMA Interrupt Status Register */ #define MTK_RX_DONE_DLY … #define MTK_TX_DONE_DLY … #define MTK_RX_DONE_INT3 … #define MTK_RX_DONE_INT2 … #define MTK_RX_DONE_INT1 … #define MTK_RX_DONE_INT0 … #define MTK_TX_DONE_INT3 … #define MTK_TX_DONE_INT2 … #define MTK_TX_DONE_INT1 … #define MTK_TX_DONE_INT0 … #define MTK_RX_DONE_INT … #define MTK_TX_DONE_INT … #define MTK_RX_DONE_INT_V2 … #define MTK_CDM_TXFIFO_RDY … /* QDMA Interrupt grouping registers */ #define MTK_RLS_DONE_INT … /* QDMA TX NUM */ #define QID_BITS_V2(x) … #define MTK_QDMA_GMAC2_QID … #define MTK_TX_DMA_BUF_SHIFT … /* QDMA V2 descriptor txd6 */ #define TX_DMA_INS_VLAN_V2 … /* QDMA V2 descriptor txd5 */ #define TX_DMA_CHKSUM_V2 … #define TX_DMA_TSO_V2 … #define TX_DMA_SPTAG_V3 … /* QDMA V2 descriptor txd4 */ #define TX_DMA_FPORT_SHIFT_V2 … #define TX_DMA_FPORT_MASK_V2 … #define TX_DMA_SWC_V2 … /* QDMA descriptor txd4 */ #define TX_DMA_CHKSUM … #define TX_DMA_TSO … #define TX_DMA_FPORT_SHIFT … #define TX_DMA_FPORT_MASK … #define TX_DMA_INS_VLAN … /* QDMA descriptor txd3 */ #define TX_DMA_OWNER_CPU … #define TX_DMA_LS0 … #define TX_DMA_PLEN0(x) … #define TX_DMA_PLEN1(x) … #define TX_DMA_SWC … #define TX_DMA_PQID … #define TX_DMA_ADDR64_MASK … #if IS_ENABLED(CONFIG_64BIT) #define TX_DMA_GET_ADDR64(x) … #define TX_DMA_PREP_ADDR64(x) … #else #define TX_DMA_GET_ADDR64 … #define TX_DMA_PREP_ADDR64 … #endif /* PDMA on MT7628 */ #define TX_DMA_DONE … #define TX_DMA_LS1 … #define TX_DMA_DESP2_DEF … /* QDMA descriptor rxd2 */ #define RX_DMA_DONE … #define RX_DMA_LSO … #define RX_DMA_PREP_PLEN0(x) … #define RX_DMA_GET_PLEN0(x) … #define RX_DMA_VTAG … #define RX_DMA_ADDR64_MASK … #if IS_ENABLED(CONFIG_64BIT) #define RX_DMA_GET_ADDR64(x) … #define RX_DMA_PREP_ADDR64(x) … #else #define RX_DMA_GET_ADDR64 … #define RX_DMA_PREP_ADDR64 … #endif /* QDMA descriptor rxd3 */ #define RX_DMA_VID(x) … #define RX_DMA_TCI(x) … #define RX_DMA_VPID(x) … /* QDMA descriptor rxd4 */ #define MTK_RXD4_FOE_ENTRY … #define MTK_RXD4_PPE_CPU_REASON … #define MTK_RXD4_SRC_PORT … #define MTK_RXD4_ALG … /* QDMA descriptor rxd4 */ #define RX_DMA_L4_VALID … #define RX_DMA_L4_VALID_PDMA … #define RX_DMA_SPECIAL_TAG … /* PDMA descriptor rxd5 */ #define MTK_RXD5_FOE_ENTRY … #define MTK_RXD5_PPE_CPU_REASON … #define MTK_RXD5_SRC_PORT … #define RX_DMA_GET_SPORT(x) … #define RX_DMA_GET_SPORT_V2(x) … /* PDMA V2 descriptor rxd3 */ #define RX_DMA_VTAG_V2 … #define RX_DMA_L4_VALID_V2 … /* PHY Polling and SMI Master Control registers */ #define MTK_PPSC … #define PPSC_MDC_CFG … #define PPSC_MDC_TURBO … #define MDC_MAX_FREQ … #define MDC_MAX_DIVIDER … /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC … #define PHY_IAC_ACCESS … #define PHY_IAC_REG_MASK … #define PHY_IAC_REG(x) … #define PHY_IAC_ADDR_MASK … #define PHY_IAC_ADDR(x) … #define PHY_IAC_CMD_MASK … #define PHY_IAC_CMD_C45_ADDR … #define PHY_IAC_CMD_WRITE … #define PHY_IAC_CMD_C22_READ … #define PHY_IAC_CMD_C45_READ … #define PHY_IAC_START_MASK … #define PHY_IAC_START_C45 … #define PHY_IAC_START_C22 … #define PHY_IAC_DATA_MASK … #define PHY_IAC_DATA(x) … #define PHY_IAC_TIMEOUT … #define MTK_MAC_MISC … #define MTK_MAC_MISC_V3 … #define MTK_MUX_TO_ESW … #define MISC_MDC_TURBO … /* XMAC status registers */ #define MTK_XGMAC_STS(x) … #define MTK_XGMAC_FORCE_LINK(x) … #define MTK_USXGMII_PCS_LINK … #define MTK_XGMAC_RX_FC … #define MTK_XGMAC_TX_FC … #define MTK_USXGMII_PCS_MODE … #define MTK_XGMAC_LINK_STS … /* GSW bridge registers */ #define MTK_GSW_CFG … #define GSWTX_IPG_MASK … #define GSWTX_IPG_SHIFT … #define GSWRX_IPG_MASK … #define GSWRX_IPG_SHIFT … #define GSW_IPG_11 … /* Mac control registers */ #define MTK_MAC_MCR(x) … #define MAC_MCR_MAX_RX_MASK … #define MAC_MCR_MAX_RX(_x) … #define MAC_MCR_MAX_RX_1518 … #define MAC_MCR_MAX_RX_1536 … #define MAC_MCR_MAX_RX_1552 … #define MAC_MCR_MAX_RX_2048 … #define MAC_MCR_IPG_CFG … #define MAC_MCR_FORCE_MODE … #define MAC_MCR_TX_EN … #define MAC_MCR_RX_EN … #define MAC_MCR_RX_FIFO_CLR_DIS … #define MAC_MCR_BACKOFF_EN … #define MAC_MCR_BACKPR_EN … #define MAC_MCR_FORCE_RX_FC … #define MAC_MCR_FORCE_TX_FC … #define MAC_MCR_SPEED_1000 … #define MAC_MCR_SPEED_100 … #define MAC_MCR_FORCE_DPX … #define MAC_MCR_FORCE_LINK … #define MAC_MCR_FORCE_LINK_DOWN … /* Mac status registers */ #define MTK_MAC_MSR(x) … #define MAC_MSR_EEE1G … #define MAC_MSR_EEE100M … #define MAC_MSR_RX_FC … #define MAC_MSR_TX_FC … #define MAC_MSR_SPEED_1000 … #define MAC_MSR_SPEED_100 … #define MAC_MSR_SPEED_MASK … #define MAC_MSR_DPX … #define MAC_MSR_LINK … /* TRGMII RXC control register */ #define TRGMII_RCK_CTRL … #define DQSI0(x) … #define DQSI1(x) … #define RXCTL_DMWTLAT(x) … #define RXC_RST … #define RXC_DQSISEL … #define RCK_CTRL_RGMII_1000 … #define RCK_CTRL_RGMII_10_100 … #define NUM_TRGMII_CTRL … /* TRGMII RXC control register */ #define TRGMII_TCK_CTRL … #define TXCTL_DMWTLAT(x) … #define TXC_INV … #define TCK_CTRL_RGMII_1000 … #define TCK_CTRL_RGMII_10_100 … /* TRGMII TX Drive Strength */ #define TRGMII_TD_ODT(i) … #define TD_DM_DRVP(x) … #define TD_DM_DRVN(x) … /* TRGMII Interface mode register */ #define INTF_MODE … #define TRGMII_INTF_DIS … #define TRGMII_MODE … #define TRGMII_CENTRAL_ALIGNED … #define INTF_MODE_RGMII_1000 … #define INTF_MODE_RGMII_10_100 … /* GPIO port control registers for GMAC 2*/ #define GPIO_OD33_CTRL8 … #define GPIO_BIAS_CTRL … #define GPIO_DRV_SEL10 … /* ethernet subsystem chip id register */ #define ETHSYS_CHIPID0_3 … #define ETHSYS_CHIPID4_7 … #define MT7623_ETH … #define MT7622_ETH … #define MT7621_ETH … /* ethernet system control register */ #define ETHSYS_SYSCFG … #define SYSCFG_DRAM_TYPE_DDR2 … /* ethernet subsystem config register */ #define ETHSYS_SYSCFG0 … #define SYSCFG0_GE_MASK … #define SYSCFG0_GE_MODE(x, y) … #define SYSCFG0_SGMII_MASK … #define SYSCFG0_SGMII_GMAC1 … #define SYSCFG0_SGMII_GMAC2 … #define SYSCFG0_SGMII_GMAC1_V2 … #define SYSCFG0_SGMII_GMAC2_V2 … /* ethernet subsystem clock register */ #define ETHSYS_CLKCFG0 … #define ETHSYS_TRGMII_CLK_SEL362_5 … #define ETHSYS_TRGMII_MT7621_MASK … #define ETHSYS_TRGMII_MT7621_APLL … #define ETHSYS_TRGMII_MT7621_DDR_PLL … /* ethernet reset control register */ #define ETHSYS_RSTCTRL … #define RSTCTRL_FE … #define RSTCTRL_WDMA0 … #define RSTCTRL_WDMA1 … #define RSTCTRL_WDMA2 … #define RSTCTRL_PPE0 … #define RSTCTRL_PPE0_V2 … #define RSTCTRL_PPE1 … #define RSTCTRL_PPE0_V3 … #define RSTCTRL_PPE1_V3 … #define RSTCTRL_PPE2 … #define RSTCTRL_ETH … /* ethernet reset check idle register */ #define ETHSYS_FE_RST_CHK_IDLE_EN … /* ethernet dma channel agent map */ #define ETHSYS_DMA_AG_MAP … #define ETHSYS_DMA_AG_MAP_PDMA … #define ETHSYS_DMA_AG_MAP_QDMA … #define ETHSYS_DMA_AG_MAP_PPE … /* Infrasys subsystem config registers */ #define INFRA_MISC2 … #define CO_QPHY_SEL … #define GEPHY_MAC_SEL … /* Top misc registers */ #define USB_PHY_SWITCH_REG … #define QPHY_SEL_MASK … #define SGMII_QPHY_SEL … /* MT7628/88 specific stuff */ #define MT7628_PDMA_OFFSET … #define MT7628_SDM_OFFSET … #define MT7628_TX_BASE_PTR0 … #define MT7628_TX_MAX_CNT0 … #define MT7628_TX_CTX_IDX0 … #define MT7628_TX_DTX_IDX0 … #define MT7628_PST_DTX_IDX0 … #define MT7628_SDM_MAC_ADRL … #define MT7628_SDM_MAC_ADRH … /* Counter / stat register */ #define MT7628_SDM_TPCNT … #define MT7628_SDM_TBCNT … #define MT7628_SDM_RPCNT … #define MT7628_SDM_RBCNT … #define MT7628_SDM_CS_ERR … #define MTK_FE_CDM1_FSM … #define MTK_FE_CDM2_FSM … #define MTK_FE_CDM3_FSM … #define MTK_FE_CDM4_FSM … #define MTK_FE_CDM5_FSM … #define MTK_FE_CDM6_FSM … #define MTK_FE_GDM1_FSM … #define MTK_FE_GDM2_FSM … #define MTK_MAC_FSM(x) … struct mtk_rx_dma { … } __packed __aligned(…); struct mtk_rx_dma_v2 { … } __packed __aligned(…); struct mtk_tx_dma { … } __packed __aligned(…); struct mtk_tx_dma_v2 { … } __packed __aligned(…); struct mtk_eth; struct mtk_mac; struct mtk_xdp_stats { … }; /* struct mtk_hw_stats - the structure that holds the traffic statistics. * @stats_lock: make sure that stats operations are atomic * @reg_offset: the status register offset of the SoC * @syncp: the refcount * * All of the supported SoCs have hardware counters for traffic statistics. * Whenever the status IRQ triggers we can read the latest stats from these * counters and store them in this struct. */ struct mtk_hw_stats { … }; enum mtk_tx_flags { … }; /* This enum allows us to identify how the clock is defined on the array of the * clock in the order */ enum mtk_clks_map { … }; #define MT7623_CLKS_BITMAP … #define MT7622_CLKS_BITMAP … #define MT7621_CLKS_BITMAP … #define MT7628_CLKS_BITMAP … #define MT7629_CLKS_BITMAP … #define MT7981_CLKS_BITMAP … #define MT7986_CLKS_BITMAP … #define MT7988_CLKS_BITMAP … enum mtk_dev_state { … }; /* PSE Port Definition */ enum mtk_pse_port { … }; /* GMAC Identifier */ enum mtk_gmac_id { … }; enum mtk_tx_buf_type { … }; /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at * by the TX descriptor s * @skb: The SKB pointer of the packet being sent * @dma_addr0: The base addr of the first segment * @dma_len0: The length of the first segment * @dma_addr1: The base addr of the second segment * @dma_len1: The length of the second segment */ struct mtk_tx_buf { … }; /* struct mtk_tx_ring - This struct holds info describing a TX ring * @dma: The descriptor ring * @buf: The memory pointed at by the ring * @phys: The physical addr of tx_buf * @next_free: Pointer to the next free descriptor * @last_free: Pointer to the last free descriptor * @last_free_ptr: Hardware pointer value of the last free descriptor * @thresh: The threshold of minimum amount of free descriptors * @free_count: QDMA uses a linked list. Track how many free descriptors * are present */ struct mtk_tx_ring { … }; /* PDMA rx ring mode */ enum mtk_rx_flags { … }; /* struct mtk_rx_ring - This struct holds info describing a RX ring * @dma: The descriptor ring * @data: The memory pointed at by the ring * @phys: The physical addr of rx_buf * @frag_size: How big can each fragment be * @buf_size: The size of each packet buffer * @calc_idx: The current head of ring */ struct mtk_rx_ring { … }; enum mkt_eth_capabilities { … }; /* Supported hardware group on SoCs */ #define MTK_RGMII … #define MTK_TRGMII … #define MTK_SGMII … #define MTK_ESW … #define MTK_GEPHY … #define MTK_MUX … #define MTK_INFRA … #define MTK_SHARED_SGMII … #define MTK_HWLRO … #define MTK_SHARED_INT … #define MTK_TRGMII_MT7621_CLK … #define MTK_QDMA … #define MTK_SOC_MT7628 … #define MTK_RSTCTRL_PPE1 … #define MTK_RSTCTRL_PPE2 … #define MTK_U3_COPHY_V2 … #define MTK_SRAM … #define MTK_36BIT_DMA … #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW … #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY … #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY … #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII … #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII … /* Supported path present on SoCs */ #define MTK_ETH_PATH_GMAC1_RGMII … #define MTK_ETH_PATH_GMAC1_TRGMII … #define MTK_ETH_PATH_GMAC1_SGMII … #define MTK_ETH_PATH_GMAC2_RGMII … #define MTK_ETH_PATH_GMAC2_SGMII … #define MTK_ETH_PATH_GMAC2_GEPHY … #define MTK_ETH_PATH_GDM1_ESW … #define MTK_GMAC1_RGMII … #define MTK_GMAC1_TRGMII … #define MTK_GMAC1_SGMII … #define MTK_GMAC2_RGMII … #define MTK_GMAC2_SGMII … #define MTK_GMAC2_GEPHY … #define MTK_GDM1_ESW … /* MUXes present on SoCs */ /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ #define MTK_MUX_GDM1_TO_GMAC1_ESW … /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY … /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ #define MTK_MUX_U3_GMAC2_TO_QPHY … /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII … /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ #define MTK_MUX_GMAC12_TO_GEPHY_SGMII … #define MTK_HAS_CAPS(caps, _x) … #define MT7621_CAPS … #define MT7622_CAPS … #define MT7623_CAPS … #define MT7628_CAPS … #define MT7629_CAPS … #define MT7981_CAPS … #define MT7986_CAPS … #define MT7988_CAPS … struct mtk_tx_dma_desc_info { … }; struct mtk_reg_map { … }; /* struct mtk_eth_data - This is the structure holding all differences * among various plaforms * @reg_map Soc register map. * @ana_rgc3: The offset for register ANA_RGC3 related to * sgmiisys syscon * @caps Flags shown the extra capability for the SoC * @hw_features Flags shown HW features * @required_clks Flags shown the bitmap for required clocks on * the target SoC * @required_pctl A bool value to show whether the SoC requires * the extra setup for those pins used by GMAC. * @hash_offset Flow table hash offset. * @version SoC version. * @foe_entry_size Foe table entry size. * @has_accounting Bool indicating support for accounting of * offloaded flows. * @desc_size Tx/Rx DMA descriptor size. * @irq_done_mask Rx irq done register mask. * @dma_l4_valid Rx DMA valid register mask. * @dma_max_len Max DMA tx/rx buffer length. * @dma_len_offset Tx/Rx DMA length field offset. */ struct mtk_soc_data { … }; #define MTK_DMA_MONITOR_TIMEOUT … /* currently no SoC has more than 3 macs */ #define MTK_MAX_DEVS … /* struct mtk_eth - This is the main datasructure for holding the state * of the driver * @dev: The device pointer * @dev: The device pointer used for dma mapping/alloc * @base: The mapped register i/o base * @page_lock: Make sure that register operations are atomic * @tx_irq__lock: Make sure that IRQ register operations are atomic * @rx_irq__lock: Make sure that IRQ register operations are atomic * @dim_lock: Make sure that Net DIM operations are atomic * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a * dummy for NAPI to work * @netdev: The netdev instances * @mac: Each netdev is linked to a physical MAC * @irq: The IRQ that we are using * @msg_enable: Ethtool msg level * @ethsys: The register map pointing at the range used to setup * MII modes * @infra: The register map pointing at the range used to setup * SGMII and GePHY path * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances * @pctl: The register map pointing at the range used to setup * GMAC port drive/slew values * @dma_refcnt: track how many netdevs are using the DMA engine * @tx_ring: Pointer to the memory holding info about the TX ring * @rx_ring: Pointer to the memory holding info about the RX ring * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring * @tx_napi: The TX NAPI struct * @rx_napi: The RX NAPI struct * @rx_events: Net DIM RX event counter * @rx_packets: Net DIM RX packet counter * @rx_bytes: Net DIM RX byte counter * @rx_dim: Net DIM RX context * @tx_events: Net DIM TX event counter * @tx_packets: Net DIM TX packet counter * @tx_bytes: Net DIM TX byte counter * @tx_dim: Net DIM TX context * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring * @phy_scratch_ring: physical address of scratch_ring * @scratch_head: The scratch memory that scratch_ring points to. * @clks: clock array for all clocks required * @mii_bus: If there is a bus we need to create an instance for it * @pending_work: The workqueue used to reset the dma ring * @state: Initialization and runtime state of the device * @soc: Holding specific data among vaious SoCs */ struct mtk_eth { … }; /* struct mtk_mac - the structure that holds the info about the MACs of the * SoC * @id: The number of the MAC * @interface: Interface mode kept for detecting change in hw settings * @of_node: Our devicetree node * @hw: Backpointer to our main datastruture * @hw_stats: Packet statistics counter */ struct mtk_mac { … }; /* the struct describing the SoC. these are declared in the soc_xyz.c files */ extern const struct of_device_id of_mtk_match[]; static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) { … } static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) { … } static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) { … } static inline struct mtk_foe_entry * mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) { … } static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) { … } static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) { … } static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) { … } static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) { … } static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) { … } static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) { … } static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) { … } static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) { … } static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) { … } /* read the hardware status register */ void mtk_stats_update_mac(struct mtk_mac *mac); void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); u32 mtk_r32(struct mtk_eth *eth, unsigned reg); u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); int mtk_eth_offload_init(struct mtk_eth *eth, u8 id); int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls, int ppe_index); void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); #endif /* MTK_ETH_H */
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