// SPDX-License-Identifier: GPL-2.0-only /* Copyright (C) 2020 Felix Fietkau <[email protected]> */ #ifndef __MTK_WED_REGS_H #define __MTK_WED_REGS_H #define MTK_WFDMA_DESC_CTRL_TO_HOST … #define MTK_WDMA_DESC_CTRL_LEN1 … #define MTK_WDMA_DESC_CTRL_LEN1_V2 … #define MTK_WDMA_DESC_CTRL_LAST_SEG1 … #define MTK_WDMA_DESC_CTRL_BURST … #define MTK_WDMA_DESC_CTRL_LEN0 … #define MTK_WDMA_DESC_CTRL_LAST_SEG0 … #define MTK_WDMA_DESC_CTRL_DMA_DONE … #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE … #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE … struct mtk_wdma_desc { … } __packed __aligned(…); #define MTK_WED_REV_ID … #define MTK_WED_RESET … #define MTK_WED_RESET_TX_BM … #define MTK_WED_RESET_RX_BM … #define MTK_WED_RESET_RX_PG_BM … #define MTK_WED_RESET_RRO_RX_TO_PG … #define MTK_WED_RESET_TX_FREE_AGENT … #define MTK_WED_RESET_WPDMA_TX_DRV … #define MTK_WED_RESET_WPDMA_RX_DRV … #define MTK_WED_RESET_WPDMA_RX_D_DRV … #define MTK_WED_RESET_WPDMA_INT_AGENT … #define MTK_WED_RESET_WED_TX_DMA … #define MTK_WED_RESET_WED_RX_DMA … #define MTK_WED_RESET_WDMA_TX_DRV … #define MTK_WED_RESET_WDMA_RX_DRV … #define MTK_WED_RESET_WDMA_INT_AGENT … #define MTK_WED_RESET_RX_RRO_QM … #define MTK_WED_RESET_RX_ROUTE_QM … #define MTK_WED_RESET_TX_AMSDU … #define MTK_WED_RESET_WED … #define MTK_WED_CTRL … #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN … #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY … #define MTK_WED_CTRL_WDMA_INT_AGENT_EN … #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY … #define MTK_WED_CTRL_WED_RX_IND_CMD_EN … #define MTK_WED_CTRL_WED_RX_PG_BM_EN … #define MTK_WED_CTRL_WED_RX_PG_BM_BUSY … #define MTK_WED_CTRL_WED_TX_BM_EN … #define MTK_WED_CTRL_WED_TX_BM_BUSY … #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN … #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY … #define MTK_WED_CTRL_WED_RX_BM_EN … #define MTK_WED_CTRL_WED_RX_BM_BUSY … #define MTK_WED_CTRL_RX_RRO_QM_EN … #define MTK_WED_CTRL_RX_RRO_QM_BUSY … #define MTK_WED_CTRL_RX_ROUTE_QM_EN … #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY … #define MTK_WED_CTRL_TX_TKID_ALI_EN … #define MTK_WED_CTRL_TX_TKID_ALI_BUSY … #define MTK_WED_CTRL_TX_AMSDU_EN … #define MTK_WED_CTRL_TX_AMSDU_BUSY … #define MTK_WED_CTRL_FINAL_DIDX_READ … #define MTK_WED_CTRL_ETH_DMAD_FMT … #define MTK_WED_CTRL_MIB_READ_CLEAR … #define MTK_WED_CTRL_FLD_MIB_RD_CLR … #define MTK_WED_EXT_INT_STATUS … #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR … #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD … #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID … #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH … #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH … #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH … #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH … #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR … #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR … #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT … #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN … #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT … #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR … #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR … #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR … #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE … #define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP … #define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR … #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY … #define MTK_WED_EXT_INT_STATUS_ERROR_MASK … #define MTK_WED_EXT_INT_MASK … #define MTK_WED_EXT_INT_MASK1 … #define MTK_WED_EXT_INT_MASK2 … #define MTK_WED_EXT_INT_MASK3 … #define MTK_WED_STATUS … #define MTK_WED_STATUS_TX … #define MTK_WED_WPDMA_STATUS … #define MTK_WED_WPDMA_STATUS_TX_DRV … #define MTK_WED_TX_BM_CTRL … #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM … #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM … #define MTK_WED_TX_BM_CTRL_LEGACY_EN … #define MTK_WED_TX_TKID_CTRL_FREE_FORMAT … #define MTK_WED_TX_BM_CTRL_PAUSE … #define MTK_WED_TX_BM_BASE … #define MTK_WED_TX_BM_INIT_PTR … #define MTK_WED_TX_BM_SW_TAIL_IDX … #define MTK_WED_TX_BM_INIT_SW_TAIL_IDX … #define MTK_WED_TX_BM_TKID_START … #define MTK_WED_TX_BM_TKID_END … #define MTK_WED_TX_BM_BUF_LEN … #define MTK_WED_TX_BM_INTF … #define MTK_WED_TX_BM_INTF_TKID … #define MTK_WED_TX_BM_INTF_TKFIFO_FDEP … #define MTK_WED_TX_BM_INTF_TKID_VALID … #define MTK_WED_TX_BM_INTF_TKID_READ … #define MTK_WED_TX_BM_DYN_THR … #define MTK_WED_TX_BM_DYN_THR_LO … #define MTK_WED_TX_BM_DYN_THR_LO_V2 … #define MTK_WED_TX_BM_DYN_THR_HI … #define MTK_WED_TX_BM_DYN_THR_HI_V2 … #define MTK_WED_TX_TKID_CTRL … #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM … #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM … #define MTK_WED_TX_TKID_CTRL_PAUSE … #define MTK_WED_TX_TKID_INTF … #define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP … #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 … #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 … #define MTK_WED_TX_TKID_DYN_THR … #define MTK_WED_TX_TKID_DYN_THR_LO … #define MTK_WED_TX_TKID_DYN_THR_HI … #define MTK_WED_TXP_DW0 … #define MTK_WED_TXP_DW1 … #define MTK_WED_WPDMA_WRITE_TXP … #define MTK_WED_TXDP_CTRL … #define MTK_WED_TXDP_DW9_OVERWR … #define MTK_WED_RX_BM_TKID_MIB … #define MTK_WED_INT_STATUS … #define MTK_WED_INT_MASK … #define MTK_WED_GLO_CFG … #define MTK_WED_GLO_CFG_TX_DMA_EN … #define MTK_WED_GLO_CFG_TX_DMA_BUSY … #define MTK_WED_GLO_CFG_RX_DMA_EN … #define MTK_WED_GLO_CFG_RX_DMA_BUSY … #define MTK_WED_GLO_CFG_RX_BT_SIZE … #define MTK_WED_GLO_CFG_TX_WB_DDONE … #define MTK_WED_GLO_CFG_BIG_ENDIAN … #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN … #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO … #define MTK_WED_GLO_CFG_MULTI_DMA_EN … #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN … #define MTK_WED_GLO_CFG_MI_DEPTH_RD … #define MTK_WED_GLO_CFG_TX_BT_SIZE_HI … #define MTK_WED_GLO_CFG_SW_RESET … #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY … #define MTK_WED_GLO_CFG_OMIT_RX_INFO … #define MTK_WED_GLO_CFG_OMIT_TX_INFO … #define MTK_WED_GLO_CFG_BYTE_SWAP … #define MTK_WED_GLO_CFG_RX_2B_OFFSET … #define MTK_WED_RESET_IDX … #define MTK_WED_RESET_WPDMA_IDX_RX … #define MTK_WED_TX_MIB(_n) … #define MTK_WED_RX_MIB(_n) … #define MTK_WED_RING_TX(_n) … #define MTK_WED_RING_RX(_n) … #define MTK_WED_RING_RX_DATA(_n) … #define MTK_WED_SCR0 … #define MTK_WED_RX1_CTRL2 … #define MTK_WED_WPDMA_INT_TRIGGER … #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE … #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE … #define MTK_WED_WPDMA_GLO_CFG … #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN … #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY … #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE … #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE … #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN … #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN … #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO … #define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN … #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN … #define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD … #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI … #define MTK_WED_WPDMA_GLO_CFG_SW_RESET … #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY … #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO … #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO … #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP … #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET … /* CONFIG_MEDIATEK_NETSYS_V2 */ #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT … #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK … #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR … #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP … #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST … #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV … #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK … #define MTK_WED_WPDMA_RESET_IDX … #define MTK_WED_WPDMA_RESET_IDX_TX … #define MTK_WED_WPDMA_RESET_IDX_RX … #define MTK_WED_WPDMA_CTRL … #define MTK_WED_WPDMA_CTRL_SDL1_FIXED … #define MTK_WED_WPDMA_INT_CTRL … #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV … #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC … #define MTK_WED_WPDMA_INT_CTRL_SRC_SEL … #define MTK_WED_WPDMA_INT_MASK … #define MTK_WED_WPDMA_INT_CTRL_TX … #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN … #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR … #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN … #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR … #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RX … #define MTK_WED_WPDMA_INT_CTRL_RX0_EN … #define MTK_WED_WPDMA_INT_CTRL_RX0_CLR … #define MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RX1_EN … #define MTK_WED_WPDMA_INT_CTRL_RX1_CLR … #define MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_TX_FREE … #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN … #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR … #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG … #define MTK_WED_PCIE_CFG_BASE … #define MTK_WED_PCIE_CFG_BASE … #define MTK_WED_PCIE_CFG_INTM … #define MTK_WED_PCIE_CFG_MSIS … #define MTK_WED_PCIE_INT_TRIGGER … #define MTK_WED_PCIE_INT_TRIGGER_STATUS … #define MTK_WED_PCIE_INT_CTRL … #define MTK_WED_PCIE_INT_CTRL_POLL_EN … #define MTK_WED_PCIE_INT_CTRL_SRC_SEL … #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA … #define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER … #define MTK_WED_WPDMA_CFG_BASE … #define MTK_WED_WPDMA_CFG_INT_MASK … #define MTK_WED_WPDMA_CFG_TX … #define MTK_WED_WPDMA_CFG_TX_FREE … #define MTK_WED_WPDMA_TX_MIB(_n) … #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) … #define MTK_WED_WPDMA_RX_MIB(_n) … #define MTK_WED_WPDMA_RX_COHERENT_MIB(_n) … #define MTK_WED_WPDMA_RING_TX(_n) … #define MTK_WED_WPDMA_RING_RX(_n) … #define MTK_WED_WPDMA_RING_RX_DATA(_n) … #define MTK_WED_WPDMA_RX_D_GLO_CFG … #define MTK_WED_WPDMA_RX_D_RX_DRV_EN … #define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY … #define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE … #define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE … #define MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL … #define MTK_WED_WPDMA_RX_D_RXD_READ_LEN … #define MTK_WED_WPDMA_RX_D_RST_IDX … #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX … #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL … #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX … #define MTK_WED_WPDMA_RX_GLO_CFG … #define MTK_WED_WPDMA_RX_D_MIB(_n) … #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) … #define MTK_WED_WPDMA_RX_D_COHERENT_MIB … #define MTK_WED_WPDMA_RX_D_PREF_CFG … #define MTK_WED_WPDMA_RX_D_PREF_EN … #define MTK_WED_WPDMA_RX_D_PREF_BUSY … #define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE … #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES … #define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX … #define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR … #define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX … #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG … #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR … #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR … #define MTK_WED_WDMA_RING_TX … #define MTK_WED_WDMA_TX_MIB … #define MTK_WED_WDMA_RING_RX(_n) … #define MTK_WED_WDMA_RX_THRES(_n) … #define MTK_WED_WDMA_RX_PREF_CFG … #define MTK_WED_WDMA_RX_PREF_EN … #define MTK_WED_WDMA_RX_PREF_BUSY … #define MTK_WED_WDMA_RX_PREF_BURST_SIZE … #define MTK_WED_WDMA_RX_PREF_LOW_THRES … #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR … #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR … #define MTK_WED_WDMA_RX_PREF_DDONE2_EN … #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY … #define MTK_WED_WDMA_RX_PREF_FIFO_CFG … #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR … #define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR … #define MTK_WED_WDMA_GLO_CFG … #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN … #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK … #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN … #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY … #define MTK_WED_WDMA_GLO_CFG_BT_SIZE … #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE … #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE … #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL … #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS … #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS … #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE … #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT … #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW … #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W … #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY … #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP … #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE … #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE … #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS … #define MTK_WED_WDMA_RESET_IDX … #define MTK_WED_WDMA_RESET_IDX_RX … #define MTK_WED_WDMA_RESET_IDX_RX_ALL … #define MTK_WED_WDMA_RESET_IDX_DRV … #define MTK_WED_WDMA_INT_CLR … #define MTK_WED_WDMA_INT_CLR_RX_DONE … #define MTK_WED_WDMA_INT_TRIGGER … #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE … #define MTK_WED_WDMA_INT_CTRL … #define MTK_WED_WDMA_INT_POLL_PRD … #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL … #define MTK_WED_WDMA_CFG_BASE … #define MTK_WED_WDMA_OFFSET0 … #define MTK_WED_WDMA_OFFSET1 … #define MTK_WED_WDMA_OFST0_GLO_INTS … #define MTK_WED_WDMA_OFST0_GLO_CFG … #define MTK_WED_WDMA_OFST1_TX_CTRL … #define MTK_WED_WDMA_OFST1_RX_CTRL … #define MTK_WED_WDMA_RX_MIB(_n) … #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) … #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) … #define MTK_WED_RX_BM_RX_DMAD … #define MTK_WED_RX_BM_RX_DMAD_SDL0 … #define MTK_WED_RX_BM_BASE … #define MTK_WED_RX_BM_INIT_PTR … #define MTK_WED_RX_BM_SW_TAIL … #define MTK_WED_RX_BM_INIT_SW_TAIL … #define MTK_WED_RX_PTR … #define MTK_WED_RX_BM_DYN_ALLOC_TH … #define MTK_WED_RX_BM_DYN_ALLOC_TH_H … #define MTK_WED_RX_BM_DYN_ALLOC_TH_L … #define MTK_WED_RING_OFS_BASE … #define MTK_WED_RING_OFS_COUNT … #define MTK_WED_RING_OFS_CPU_IDX … #define MTK_WED_RING_OFS_DMA_IDX … #define MTK_WDMA_RING_TX(_n) … #define MTK_WDMA_RING_RX(_n) … #define MTK_WDMA_GLO_CFG … #define MTK_WDMA_GLO_CFG_TX_DMA_EN … #define MTK_WDMA_GLO_CFG_TX_DMA_BUSY … #define MTK_WDMA_GLO_CFG_RX_DMA_EN … #define MTK_WDMA_GLO_CFG_RX_DMA_BUSY … #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES … #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES … #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES … #define MTK_WDMA_RESET_IDX … #define MTK_WDMA_RESET_IDX_TX … #define MTK_WDMA_RESET_IDX_RX … #define MTK_WDMA_INT_STATUS … #define MTK_WDMA_INT_MASK … #define MTK_WDMA_INT_MASK_TX_DONE … #define MTK_WDMA_INT_MASK_RX_DONE … #define MTK_WDMA_INT_MASK_TX_DELAY … #define MTK_WDMA_INT_MASK_TX_COHERENT … #define MTK_WDMA_INT_MASK_RX_DELAY … #define MTK_WDMA_INT_MASK_RX_COHERENT … #define MTK_WDMA_XDMA_TX_FIFO_CFG … #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR … #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR … #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR … #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR … #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR … #define MTK_WDMA_INT_GRP1 … #define MTK_WDMA_INT_GRP2 … #define MTK_WDMA_PREF_TX_CFG … #define MTK_WDMA_PREF_TX_CFG_PREF_EN … #define MTK_WDMA_PREF_TX_CFG_PREF_BUSY … #define MTK_WDMA_PREF_RX_CFG … #define MTK_WDMA_PREF_RX_CFG_PREF_EN … #define MTK_WDMA_PREF_RX_CFG_PREF_BUSY … #define MTK_WDMA_PREF_RX_FIFO_CFG … #define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR … #define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR … #define MTK_WDMA_PREF_TX_FIFO_CFG … #define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR … #define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR … #define MTK_WDMA_PREF_SIDX_CFG … #define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR … #define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR … #define MTK_WDMA_WRBK_TX_CFG … #define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY … #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN … #define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) … #define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR … #define MTK_WDMA_WRBK_RX_CFG … #define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY … #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN … #define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) … #define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR … #define MTK_WDMA_WRBK_SIDX_CFG … #define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR … #define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR … #define MTK_PCIE_MIRROR_MAP(n) … #define MTK_PCIE_MIRROR_MAP_EN … #define MTK_PCIE_MIRROR_MAP_WED_ID … /* DMA channel mapping */ #define HIFSYS_DMA_AG_MAP … #define MTK_WED_RTQM_GLO_CFG … #define MTK_WED_RTQM_BUSY … #define MTK_WED_RTQM_Q_RST … #define MTK_WED_RTQM_Q_DBG_BYPASS … #define MTK_WED_RTQM_TXDMAD_FPORT … #define MTK_WED_RTQM_RST … #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT … #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) … #define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT … #define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) … #define MTK_WED_RTQM_IGRS0_FDROP_CNT … #define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT … #define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) … #define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT … #define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) … #define MTK_WED_RTQM_IGRS1_FDROP_CNT … #define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT … #define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) … #define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT … #define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) … #define MTK_WED_RTQM_IGRS2_FDROP_CNT … #define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT … #define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) … #define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT … #define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) … #define MTK_WED_RTQM_IGRS3_FDROP_CNT … #define MTK_WED_RTQM_R2H_MIB(_n) … #define MTK_WED_RTQM_R2Q_MIB(_n) … #define MTK_WED_RTQM_Q2N_MIB … #define MTK_WED_RTQM_Q2H_MIB(_n) … #define MTK_WED_RTQM_Q2B_MIB … #define MTK_WED_RTQM_PFDBK_MIB … #define MTK_WED_RTQM_ENQ_CFG0 … #define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT … #define MTK_WED_RTQM_FDROP_MIB … #define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT … #define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT … #define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT … #define MTK_WED_RTQM_ENQ_I2N_PKT_CNT … #define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT … #define MTK_WED_RTQM_ENQ_ERR_CNT … #define MTK_WED_RTQM_DEQ_DMAD_CNT … #define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT … #define MTK_WED_RTQM_DEQ_PKT_CNT … #define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT … #define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT … #define MTK_WED_RTQM_DEQ_ERR_CNT … #define MTK_WED_RROQM_GLO_CFG … #define MTK_WED_RROQM_RST_IDX … #define MTK_WED_RROQM_RST_IDX_MIOD … #define MTK_WED_RROQM_RST_IDX_FDBK … #define MTK_WED_RROQM_MIOD_CTRL0 … #define MTK_WED_RROQM_MIOD_CTRL1 … #define MTK_WED_RROQM_MIOD_CNT … #define MTK_WED_RROQM_MIOD_CTRL2 … #define MTK_WED_RROQM_MIOD_CTRL3 … #define MTK_WED_RROQM_FDBK_CTRL0 … #define MTK_WED_RROQM_FDBK_CTRL1 … #define MTK_WED_RROQM_FDBK_CNT … #define MTK_WED_RROQM_FDBK_CTRL2 … #define MTK_WED_RROQ_BASE_L … #define MTK_WED_RROQ_BASE_H … #define MTK_WED_RROQM_MIOD_CFG … #define MTK_WED_RROQM_MIOD_MID_DW … #define MTK_WED_RROQM_MIOD_MOD_DW … #define MTK_WED_RROQM_MIOD_ENTRY_DW … #define MTK_WED_RROQM_MID_MIB … #define MTK_WED_RROQM_MOD_MIB … #define MTK_WED_RROQM_MOD_COHERENT_MIB … #define MTK_WED_RROQM_FDBK_MIB … #define MTK_WED_RROQM_FDBK_COHERENT_MIB … #define MTK_WED_RROQM_FDBK_IND_MIB … #define MTK_WED_RROQM_FDBK_ENQ_MIB … #define MTK_WED_RROQM_FDBK_ANC_MIB … #define MTK_WED_RROQM_FDBK_ANC2H_MIB … #define MTK_WED_RX_BM_RX_DMAD … #define MTK_WED_RX_BM_BASE … #define MTK_WED_RX_BM_INIT_PTR … #define MTK_WED_RX_BM_PTR … #define MTK_WED_RX_BM_PTR_HEAD … #define MTK_WED_RX_BM_PTR_TAIL … #define MTK_WED_RX_BM_BLEN … #define MTK_WED_RX_BM_STS … #define MTK_WED_RX_BM_INTF2 … #define MTK_WED_RX_BM_INTF … #define MTK_WED_RX_BM_ERR_STS … #define MTK_RRO_IND_CMD_SIGNATURE … #define MTK_RRO_IND_CMD_DMA_IDX … #define MTK_RRO_IND_CMD_MAGIC_CNT … #define MTK_WED_IND_CMD_RX_CTRL0 … #define MTK_WED_IND_CMD_PROC_IDX … #define MTK_WED_IND_CMD_PREFETCH_FREE_CNT … #define MTK_WED_IND_CMD_MAGIC_CNT … #define MTK_WED_IND_CMD_RX_CTRL1 … #define MTK_WED_IND_CMD_RX_CTRL2 … #define MTK_WED_IND_CMD_MAX_CNT … #define MTK_WED_IND_CMD_BASE_M … #define MTK_WED_RRO_CFG0 … #define MTK_WED_RRO_CFG1 … #define MTK_WED_RRO_CFG1_MAX_WIN_SZ … #define MTK_WED_RRO_CFG1_ACK_SN_BASE_M … #define MTK_WED_RRO_CFG1_PARTICL_SE_ID … #define MTK_WED_ADDR_ELEM_CFG0 … #define MTK_WED_ADDR_ELEM_CFG1 … #define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT … #define MTK_WED_ADDR_ELEM_TBL_CFG … #define MTK_WED_ADDR_ELEM_TBL_OFFSET … #define MTK_WED_ADDR_ELEM_TBL_RD_RDY … #define MTK_WED_ADDR_ELEM_TBL_WR_RDY … #define MTK_WED_ADDR_ELEM_TBL_RD … #define MTK_WED_ADDR_ELEM_TBL_WR … #define MTK_WED_RADDR_ELEM_TBL_WDATA … #define MTK_WED_RADDR_ELEM_TBL_RDATA … #define MTK_WED_PN_CHECK_CFG … #define MTK_WED_PN_CHECK_SE_ID … #define MTK_WED_PN_CHECK_RD_RDY … #define MTK_WED_PN_CHECK_WR_RDY … #define MTK_WED_PN_CHECK_RD … #define MTK_WED_PN_CHECK_WR … #define MTK_WED_PN_CHECK_WDATA_M … #define MTK_WED_PN_CHECK_IS_FIRST … #define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) … #define MTK_WED_RRO_MSDU_PG_RING2_CFG … #define MTK_WED_RRO_MSDU_PG_DRV_CLR … #define MTK_WED_RRO_MSDU_PG_DRV_EN … #define MTK_WED_RRO_MSDU_PG_CTRL0(_n) … #define MTK_WED_RRO_MSDU_PG_CTRL1(_n) … #define MTK_WED_RRO_MSDU_PG_CTRL2(_n) … #define MTK_WED_RRO_RX_D_RX(_n) … #define MTK_WED_RRO_RX_MAGIC_CNT … #define MTK_WED_RRO_RX_D_CFG(_n) … #define MTK_WED_RRO_RX_D_DRV_CLR … #define MTK_WED_RRO_RX_D_DRV_EN … #define MTK_WED_RRO_PG_BM_RX_DMAM … #define MTK_WED_RRO_PG_BM_RX_SDL0 … #define MTK_WED_RRO_PG_BM_BASE … #define MTK_WED_RRO_PG_BM_INIT_PTR … #define MTK_WED_RRO_PG_BM_SW_TAIL_IDX … #define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR … #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR … #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG … #define MTK_WED_RRO_RX_HW_STS … #define MTK_WED_RX_IND_CMD_BUSY … #define MTK_WED_RX_IND_CMD_CNT0 … #define MTK_WED_RX_IND_CMD_DBG_CNT_EN … #define MTK_WED_RX_IND_CMD_CNT(_n) … #define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT … #define MTK_WED_RX_ADDR_ELEM_CNT(_n) … #define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT … #define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT … #define MTK_WED_ADDR_ELEM_ACKSN_CNT … #define MTK_WED_RX_MSDU_PG_CNT(_n) … #define MTK_WED_RX_PN_CHK_CNT … #define MTK_WED_PN_CHK_FAIL_CNT … #define MTK_WED_WOCPU_VIEW_MIOD_BASE … #define MTK_WED_PCIE_INT_MASK … #define MTK_WED_AMSDU_FIFO … #define MTK_WED_AMSDU_IS_PRIOR0_RING … #define MTK_WED_AMSDU_STA_INFO … #define MTK_WED_AMSDU_STA_INFO_DO_INIT … #define MTK_WED_AMSDU_STA_INFO_SET_INIT … #define MTK_WED_AMSDU_STA_INFO_INIT … #define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE … #define MTK_WED_AMSDU_STA_RMVL … #define MTK_WED_AMSDU_STA_MAX_AMSDU_LEN … #define MTK_WED_AMSDU_STA_MAX_AMSDU_NUM … #define MTK_WED_AMSDU_HIFTXD_BASE_L(_n) … #define MTK_WED_AMSDU_PSE … #define MTK_WED_AMSDU_PSE_RESET … #define MTK_WED_AMSDU_HIFTXD_CFG … #define MTK_WED_AMSDU_HIFTXD_SRC … #define MTK_WED_MON_AMSDU_FIFO_DMAD … #define MTK_WED_MON_AMSDU_ENG_DMAD(_n) … #define MTK_WED_MON_AMSDU_ENG_QFPL(_n) … #define MTK_WED_MON_AMSDU_ENG_QENI(_n) … #define MTK_WED_MON_AMSDU_ENG_QENO(_n) … #define MTK_WED_MON_AMSDU_ENG_MERG(_n) … #define MTK_WED_MON_AMSDU_ENG_CNT8(_n) … #define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT … #define MTK_WED_AMSDU_ENG_MAX_PL_CNT … #define MTK_WED_MON_AMSDU_ENG_CNT9(_n) … #define MTK_WED_AMSDU_ENG_CUR_ENTRY … #define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED … #define MTK_WED_AMSDU_ENG_MAX_MSDU_MERGED … #define MTK_WED_MON_AMSDU_QMEM_STS1 … #define MTK_WED_MON_AMSDU_QMEM_CNT(_n) … #define MTK_WED_AMSDU_QMEM_FQ_CNT … #define MTK_WED_AMSDU_QMEM_SP_QCNT … #define MTK_WED_AMSDU_QMEM_TID0_QCNT … #define MTK_WED_AMSDU_QMEM_TID1_QCNT … #define MTK_WED_AMSDU_QMEM_TID2_QCNT … #define MTK_WED_AMSDU_QMEM_TID3_QCNT … #define MTK_WED_AMSDU_QMEM_TID4_QCNT … #define MTK_WED_AMSDU_QMEM_TID5_QCNT … #define MTK_WED_AMSDU_QMEM_TID6_QCNT … #define MTK_WED_AMSDU_QMEM_TID7_QCNT … #define MTK_WED_MON_AMSDU_QMEM_PTR(_n) … #define MTK_WED_AMSDU_QMEM_FQ_HEAD … #define MTK_WED_AMSDU_QMEM_SP_QHEAD … #define MTK_WED_AMSDU_QMEM_TID0_QHEAD … #define MTK_WED_AMSDU_QMEM_TID1_QHEAD … #define MTK_WED_AMSDU_QMEM_TID2_QHEAD … #define MTK_WED_AMSDU_QMEM_TID3_QHEAD … #define MTK_WED_AMSDU_QMEM_TID4_QHEAD … #define MTK_WED_AMSDU_QMEM_TID5_QHEAD … #define MTK_WED_AMSDU_QMEM_TID6_QHEAD … #define MTK_WED_AMSDU_QMEM_TID7_QHEAD … #define MTK_WED_AMSDU_QMEM_FQ_TAIL … #define MTK_WED_AMSDU_QMEM_SP_QTAIL … #define MTK_WED_AMSDU_QMEM_TID0_QTAIL … #define MTK_WED_AMSDU_QMEM_TID1_QTAIL … #define MTK_WED_AMSDU_QMEM_TID2_QTAIL … #define MTK_WED_AMSDU_QMEM_TID3_QTAIL … #define MTK_WED_AMSDU_QMEM_TID4_QTAIL … #define MTK_WED_AMSDU_QMEM_TID5_QTAIL … #define MTK_WED_AMSDU_QMEM_TID6_QTAIL … #define MTK_WED_AMSDU_QMEM_TID7_QTAIL … #define MTK_WED_MON_AMSDU_HIFTXD_FETCH_MSDU(_n) … #define MTK_WED_PCIE_BASE … #define MTK_WED_PCIE_BASE0 … #define MTK_WED_PCIE_BASE1 … #define MTK_WED_PCIE_BASE2 … #endif
Codebase Browser
linux