/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2022 Lorenzo Bianconi <[email protected]> */ #ifndef __MTK_WED_WO_H #define __MTK_WED_WO_H #include <linux/skbuff.h> #include <linux/netdevice.h> struct mtk_wed_hw; struct mtk_wed_mcu_hdr { … }; struct mtk_wed_wo_log_info { … }; enum mtk_wed_wo_event { … }; #define MTK_WED_MODULE_ID_WO … #define MTK_FW_DL_TIMEOUT … #define MTK_WOCPU_TIMEOUT … enum { … }; #define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR … #define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK … #define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK … enum { … }; enum mtk_wed_wo_state { … }; enum mtk_wed_wo_done_state { … }; enum mtk_wed_dummy_cr_idx { … }; #define MT7981_FIRMWARE_WO … #define MT7986_FIRMWARE_WO0 … #define MT7986_FIRMWARE_WO1 … #define MT7988_FIRMWARE_WO0 … #define MT7988_FIRMWARE_WO1 … #define MTK_WO_MCU_CFG_LS_BASE … #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR … #define MTK_WO_MCU_CFG_LS_FW_VER_ADDR … #define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR … #define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR … #define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR … #define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR … #define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR … #define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR … #define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR … #define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR … #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK … #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK … #define MTK_WED_WO_RING_SIZE … #define MTK_WED_WO_CMD_LEN … #define MTK_WED_WO_TXCH_NUM … #define MTK_WED_WO_RXCH_NUM … #define MTK_WED_WO_RXCH_WO_EXCEPTION … #define MTK_WED_WO_TXCH_INT_MASK … #define MTK_WED_WO_RXCH_INT_MASK … #define MTK_WED_WO_EXCEPTION_INT_MASK … #define MTK_WED_WO_ALL_INT_MASK … #define MTK_WED_WO_CCIF_BUSY … #define MTK_WED_WO_CCIF_START … #define MTK_WED_WO_CCIF_TCHNUM … #define MTK_WED_WO_CCIF_RCHNUM … #define MTK_WED_WO_CCIF_RCHNUM_MASK … #define MTK_WED_WO_CCIF_ACK … #define MTK_WED_WO_CCIF_IRQ0_MASK … #define MTK_WED_WO_CCIF_IRQ1_MASK … #define MTK_WED_WO_CCIF_DUMMY1 … #define MTK_WED_WO_CCIF_DUMMY2 … #define MTK_WED_WO_CCIF_DUMMY3 … #define MTK_WED_WO_CCIF_DUMMY4 … #define MTK_WED_WO_CCIF_SHADOW1 … #define MTK_WED_WO_CCIF_SHADOW2 … #define MTK_WED_WO_CCIF_SHADOW3 … #define MTK_WED_WO_CCIF_SHADOW4 … #define MTK_WED_WO_CCIF_DUMMY5 … #define MTK_WED_WO_CCIF_DUMMY6 … #define MTK_WED_WO_CCIF_DUMMY7 … #define MTK_WED_WO_CCIF_DUMMY8 … #define MTK_WED_WO_CCIF_SHADOW5 … #define MTK_WED_WO_CCIF_SHADOW6 … #define MTK_WED_WO_CCIF_SHADOW7 … #define MTK_WED_WO_CCIF_SHADOW8 … #define MTK_WED_WO_CTL_SD_LEN1 … #define MTK_WED_WO_CTL_LAST_SEC1 … #define MTK_WED_WO_CTL_BURST … #define MTK_WED_WO_CTL_SD_LEN0_SHIFT … #define MTK_WED_WO_CTL_SD_LEN0 … #define MTK_WED_WO_CTL_LAST_SEC0 … #define MTK_WED_WO_CTL_DMA_DONE … #define MTK_WED_WO_INFO_WINFO … struct mtk_wed_wo_memory_region { … }; struct mtk_wed_fw_region { … } __packed; struct mtk_wed_fw_trailer { … }; struct mtk_wed_wo_queue_regs { … }; struct mtk_wed_wo_queue_desc { … } __packed __aligned(…); struct mtk_wed_wo_queue_entry { … }; struct mtk_wed_wo_queue { … }; struct mtk_wed_wo { … }; static inline int mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb) { … } void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb); void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, struct sk_buff *skb); int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd, const void *data, int len, bool wait_resp); int mtk_wed_mcu_msg_update(struct mtk_wed_device *dev, int id, void *data, int len); int mtk_wed_mcu_init(struct mtk_wed_wo *wo); int mtk_wed_wo_init(struct mtk_wed_hw *hw); void mtk_wed_wo_deinit(struct mtk_wed_hw *hw); int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *dev, struct mtk_wed_wo_queue *q, struct sk_buff *skb); #endif /* __MTK_WED_WO_H */
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