// SPDX-License-Identifier: GPL-2.0-only /* Copyright (C) 2020 Felix Fietkau <[email protected]> */ #ifndef __MTK_PPE_REGS_H #define __MTK_PPE_REGS_H #define MTK_PPE_GLO_CFG … #define MTK_PPE_GLO_CFG_EN … #define MTK_PPE_GLO_CFG_TSID_EN … #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP … #define MTK_PPE_GLO_CFG_IP4_CS_DROP … #define MTK_PPE_GLO_CFG_TTL0_DROP … #define MTK_PPE_GLO_CFG_PPE_BSWAP … #define MTK_PPE_GLO_CFG_PSE_HASH_OFS … #define MTK_PPE_GLO_CFG_MCAST_TB_EN … #define MTK_PPE_GLO_CFG_FLOW_DROP_KA … #define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE … #define MTK_PPE_GLO_CFG_UDP_LITE_EN … #define MTK_PPE_GLO_CFG_UDP_LEN_DROP … #define MTK_PPE_GLO_CFG_MCAST_ENTRIES … #define MTK_PPE_GLO_CFG_BUSY … #define MTK_PPE_FLOW_CFG … #define MTK_PPE_MD_TOAP_BYP_CRSN0 … #define MTK_PPE_MD_TOAP_BYP_CRSN1 … #define MTK_PPE_MD_TOAP_BYP_CRSN2 … #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG … #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG … #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE … #define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE … #define MTK_PPE_FLOW_CFG_IP6_6RD … #define MTK_PPE_FLOW_CFG_IP4_NAT … #define MTK_PPE_FLOW_CFG_IP4_NAPT … #define MTK_PPE_FLOW_CFG_IP4_DSLITE … #define MTK_PPE_FLOW_CFG_L2_BRIDGE … #define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST … #define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG … #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL … #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY … #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY … #define MTK_PPE_IP_PROTO_CHK … #define MTK_PPE_IP_PROTO_CHK_IPV4 … #define MTK_PPE_IP_PROTO_CHK_IPV6 … #define MTK_PPE_TB_CFG … #define MTK_PPE_TB_CFG_ENTRY_NUM … #define MTK_PPE_TB_CFG_ENTRY_80B … #define MTK_PPE_TB_CFG_SEARCH_MISS … #define MTK_PPE_TB_CFG_AGE_PREBIND … #define MTK_PPE_TB_CFG_AGE_NON_L4 … #define MTK_PPE_TB_CFG_AGE_UNBIND … #define MTK_PPE_TB_CFG_AGE_TCP … #define MTK_PPE_TB_CFG_AGE_UDP … #define MTK_PPE_TB_CFG_AGE_TCP_FIN … #define MTK_PPE_TB_CFG_KEEPALIVE … #define MTK_PPE_TB_CFG_HASH_MODE … #define MTK_PPE_TB_CFG_SCAN_MODE … #define MTK_PPE_TB_CFG_HASH_DEBUG … #define MTK_PPE_TB_CFG_INFO_SEL … #define MTK_PPE_TB_TICK_SEL … #define MTK_PPE_BIND_LMT1 … #define MTK_PPE_NTU_KEEPALIVE … #define MTK_PPE_KEEPALIVE … enum { … }; enum { … }; enum { … }; #define MTK_PPE_TB_BASE … #define MTK_PPE_TB_USED … #define MTK_PPE_TB_USED_NUM … #define MTK_PPE_BIND_RATE … #define MTK_PPE_BIND_RATE_BIND … #define MTK_PPE_BIND_RATE_PREBIND … #define MTK_PPE_BIND_LIMIT0 … #define MTK_PPE_BIND_LIMIT0_QUARTER … #define MTK_PPE_BIND_LIMIT0_HALF … #define MTK_PPE_BIND_LIMIT1 … #define MTK_PPE_BIND_LIMIT1_FULL … #define MTK_PPE_BIND_LIMIT1_NON_L4 … #define MTK_PPE_KEEPALIVE … #define MTK_PPE_KEEPALIVE_TIME … #define MTK_PPE_KEEPALIVE_TIME_TCP … #define MTK_PPE_KEEPALIVE_TIME_UDP … #define MTK_PPE_UNBIND_AGE … #define MTK_PPE_UNBIND_AGE_MIN_PACKETS … #define MTK_PPE_UNBIND_AGE_DELTA … #define MTK_PPE_BIND_AGE0 … #define MTK_PPE_BIND_AGE0_DELTA_NON_L4 … #define MTK_PPE_BIND_AGE0_DELTA_UDP … #define MTK_PPE_BIND_AGE1 … #define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN … #define MTK_PPE_BIND_AGE1_DELTA_TCP … #define MTK_PPE_HASH_SEED … #define MTK_PPE_DEFAULT_CPU_PORT … #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) … #define MTK_PPE_DEFAULT_CPU_PORT1 … #define MTK_PPE_MTU_DROP … #define MTK_PPE_VLAN_MTU0 … #define MTK_PPE_VLAN_MTU0_NONE … #define MTK_PPE_VLAN_MTU0_1TAG … #define MTK_PPE_VLAN_MTU1 … #define MTK_PPE_VLAN_MTU1_2TAG … #define MTK_PPE_VLAN_MTU1_3TAG … #define MTK_PPE_VPM_TPID … #define MTK_PPE_CACHE_CTL … #define MTK_PPE_CACHE_CTL_EN … #define MTK_PPE_CACHE_CTL_LOCK_CLR … #define MTK_PPE_CACHE_CTL_REQ … #define MTK_PPE_CACHE_CTL_CLEAR … #define MTK_PPE_CACHE_CTL_CMD … #define MTK_PPE_MIB_CFG … #define MTK_PPE_MIB_CFG_EN … #define MTK_PPE_MIB_CFG_RD_CLR … #define MTK_PPE_MIB_TB_BASE … #define MTK_PPE_MIB_SER_CR … #define MTK_PPE_MIB_SER_CR_ST … #define MTK_PPE_MIB_SER_CR_ADDR … #define MTK_PPE_MIB_SER_R0 … #define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW … #define MTK_PPE_MIB_SER_R1 … #define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW … #define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH … #define MTK_PPE_MIB_SER_R2 … #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH … #define MTK_PPE_MIB_SER_R3 … #define MTK_PPE_MIB_CACHE_CTL … #define MTK_PPE_MIB_CACHE_CTL_EN … #define MTK_PPE_MIB_CACHE_CTL_FLUSH … #define MTK_PPE_SBW_CTRL … #endif
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