#include "port.h"
void mlx5_port_query_eth_autoneg(struct mlx5_core_dev *dev, u8 *an_status,
u8 *an_disable_cap, u8 *an_disable_admin)
{ … }
int mlx5_port_set_eth_ptys(struct mlx5_core_dev *dev, bool an_disable,
u32 proto_admin, bool ext)
{ … }
int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
{ … }
int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
{ … }
int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
{ … }
int mlx5e_port_query_sbpr(struct mlx5_core_dev *mdev, u32 desc, u8 dir,
u8 pool_idx, void *out, int size_out)
{ … }
int mlx5e_port_set_sbpr(struct mlx5_core_dev *mdev, u32 desc, u8 dir,
u8 pool_idx, u32 infi_size, u32 size)
{ … }
static int mlx5e_port_query_sbcm(struct mlx5_core_dev *mdev, u32 desc,
u8 pg_buff_idx, u8 dir, void *out,
int size_out)
{ … }
int mlx5e_port_set_sbcm(struct mlx5_core_dev *mdev, u32 desc, u8 pg_buff_idx,
u8 dir, u8 infi_size, u32 max_buff, u8 pool_idx)
{ … }
int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
{ … }
int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
{ … }
enum mlx5e_fec_supported_link_mode { … };
#define MLX5E_FEC_FIRST_50G_PER_LANE_MODE …
#define MLX5E_FEC_FIRST_100G_PER_LANE_MODE …
#define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link) …
static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev,
enum mlx5e_fec_supported_link_mode link_mode)
{ … }
static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
enum mlx5e_fec_supported_link_mode link_mode)
{ … }
#define MLX5E_GET_FEC_OVERRIDE_CAP(buf, link) …
static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap,
enum mlx5e_fec_supported_link_mode link_mode)
{ … }
bool mlx5e_fec_in_caps(struct mlx5_core_dev *dev, int fec_policy)
{ … }
int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
u16 *fec_configured_mode)
{ … }
int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
{ … }