// SPDX-License-Identifier: GPL-2.0+ /* * PCIe host controller driver for Xilinx Versal CPM DMA Bridge * * (C) Copyright 2019 - 2020, Xilinx, Inc. */ #include <linux/bitfield.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_pci.h> #include <linux/of_platform.h> #include "../pci.h" #include "pcie-xilinx-common.h" /* Register definitions */ #define XILINX_CPM_PCIE_REG_IDR … #define XILINX_CPM_PCIE_REG_IMR … #define XILINX_CPM_PCIE_REG_PSCR … #define XILINX_CPM_PCIE_REG_RPSC … #define XILINX_CPM_PCIE_REG_RPEFR … #define XILINX_CPM_PCIE_REG_IDRN … #define XILINX_CPM_PCIE_REG_IDRN_MASK … #define XILINX_CPM_PCIE_MISC_IR_STATUS … #define XILINX_CPM_PCIE_MISC_IR_ENABLE … #define XILINX_CPM_PCIE_MISC_IR_LOCAL … #define XILINX_CPM_PCIE_IR_STATUS … #define XILINX_CPM_PCIE_IR_ENABLE … #define XILINX_CPM_PCIE_IR_LOCAL … #define IMR(x) … #define XILINX_CPM_PCIE_IMR_ALL_MASK … #define XILINX_CPM_PCIE_IDR_ALL_MASK … #define XILINX_CPM_PCIE_IDRN_MASK … #define XILINX_CPM_PCIE_IDRN_SHIFT … /* Root Port Error FIFO Read Register definitions */ #define XILINX_CPM_PCIE_RPEFR_ERR_VALID … #define XILINX_CPM_PCIE_RPEFR_REQ_ID … #define XILINX_CPM_PCIE_RPEFR_ALL_MASK … /* Root Port Status/control Register definitions */ #define XILINX_CPM_PCIE_REG_RPSC_BEN … /* Phy Status/Control Register definitions */ #define XILINX_CPM_PCIE_REG_PSCR_LNKUP … enum xilinx_cpm_version { … }; /** * struct xilinx_cpm_variant - CPM variant information * @version: CPM version */ struct xilinx_cpm_variant { … }; /** * struct xilinx_cpm_pcie - PCIe port information * @dev: Device pointer * @reg_base: Bridge Register Base * @cpm_base: CPM System Level Control and Status Register(SLCR) Base * @intx_domain: Legacy IRQ domain pointer * @cpm_domain: CPM IRQ domain pointer * @cfg: Holds mappings of config space window * @intx_irq: legacy interrupt number * @irq: Error interrupt number * @lock: lock protecting shared register access * @variant: CPM version check pointer */ struct xilinx_cpm_pcie { … }; static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) { … } static void pcie_write(struct xilinx_cpm_pcie *port, u32 val, u32 reg) { … } static bool cpm_pcie_link_up(struct xilinx_cpm_pcie *port) { … } static void cpm_pcie_clear_err_interrupts(struct xilinx_cpm_pcie *port) { … } static void xilinx_cpm_mask_leg_irq(struct irq_data *data) { … } static void xilinx_cpm_unmask_leg_irq(struct irq_data *data) { … } static struct irq_chip xilinx_cpm_leg_irq_chip = …; /** * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid * @domain: IRQ domain * @irq: Virtual IRQ number * @hwirq: HW interrupt number * * Return: Always returns 0. */ static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } /* INTx IRQ Domain operations */ static const struct irq_domain_ops intx_domain_ops = …; static void xilinx_cpm_pcie_intx_flow(struct irq_desc *desc) { … } static void xilinx_cpm_mask_event_irq(struct irq_data *d) { … } static void xilinx_cpm_unmask_event_irq(struct irq_data *d) { … } static struct irq_chip xilinx_cpm_event_irq_chip = …; static int xilinx_cpm_pcie_event_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops event_domain_ops = …; static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) { … } #define _IC(x, s) … static const struct { … } intr_cause[32] = …; static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id) { … } static void xilinx_cpm_free_irq_domains(struct xilinx_cpm_pcie *port) { … } /** * xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain * @port: PCIe port information * * Return: '0' on success and error value on failure */ static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port) { … } static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) { … } /** * xilinx_cpm_pcie_init_port - Initialize hardware * @port: PCIe port information */ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { … } /** * xilinx_cpm_pcie_parse_dt - Parse Device tree * @port: PCIe port information * @bus_range: Bus resource * * Return: '0' on success and error value on failure */ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, struct resource *bus_range) { … } static void xilinx_cpm_free_interrupts(struct xilinx_cpm_pcie *port) { … } /** * xilinx_cpm_pcie_probe - Probe function * @pdev: Platform device pointer * * Return: '0' on success and error value on failure */ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) { … } static const struct xilinx_cpm_variant cpm_host = …; static const struct xilinx_cpm_variant cpm5_host = …; static const struct of_device_id xilinx_cpm_pcie_of_match[] = …; static struct platform_driver xilinx_cpm_pcie_driver = …; builtin_platform_driver(…) …;
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