linux/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */

#ifndef MLX5_IFC_DR_STE_V1_H
#define MLX5_IFC_DR_STE_V1_H

enum mlx5_ifc_ste_v1_modify_hdr_offset { … };

struct mlx5_ifc_ste_single_action_flow_tag_v1_bits { … };

struct mlx5_ifc_ste_single_action_modify_list_v1_bits { … };

struct mlx5_ifc_ste_single_action_remove_header_v1_bits { … };

struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits { … };

struct mlx5_ifc_ste_double_action_copy_v1_bits { … };

struct mlx5_ifc_ste_double_action_set_v1_bits { … };

struct mlx5_ifc_ste_double_action_add_v1_bits { … };

struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits { … };

struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits { … };

struct mlx5_ifc_ste_double_action_accelerated_modify_action_list_v1_bits { … };

struct mlx5_ifc_ste_match_bwc_v1_bits { … };

struct mlx5_ifc_ste_mask_and_match_v1_bits { … };

struct mlx5_ifc_ste_match_ranges_v1_bits { … };

struct mlx5_ifc_ste_eth_l2_src_v1_bits { … };

struct mlx5_ifc_ste_eth_l2_dst_v1_bits { … };

struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits { … };

struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits { … };

struct mlx5_ifc_ste_eth_l2_tnl_v1_bits { … };

struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits { … };

struct mlx5_ifc_ste_eth_l4_v1_bits { … };

struct mlx5_ifc_ste_eth_l4_misc_v1_bits { … };

struct mlx5_ifc_ste_mpls_v1_bits { … };

struct mlx5_ifc_ste_gre_v1_bits { … };

struct mlx5_ifc_ste_src_gvmi_qp_v1_bits { … };

struct mlx5_ifc_ste_icmp_v1_bits { … };

#endif /* MLX5_IFC_DR_STE_V1_H */