// SPDX-License-Identifier: GPL-2.0+ /* * APM X-Gene MSI Driver * * Copyright (c) 2014, Applied Micro Circuits Corporation * Author: Tanmay Inamdar <[email protected]> * Duc Dang <[email protected]> */ #include <linux/cpu.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/module.h> #include <linux/msi.h> #include <linux/irqchip/chained_irq.h> #include <linux/pci.h> #include <linux/platform_device.h> #include <linux/of_pci.h> #define MSI_IR0 … #define MSI_INT0 … #define IDX_PER_GROUP … #define IRQS_PER_IDX … #define NR_HW_IRQS … #define NR_MSI_VEC … struct xgene_msi_group { … }; struct xgene_msi { … }; /* Global data */ static struct xgene_msi xgene_msi_ctrl; static struct irq_chip xgene_msi_top_irq_chip = …; static struct msi_domain_info xgene_msi_domain_info = …; /* * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where * n is group number (0..F), x is index of registers in each group (0..7) * The register layout is as follows: * MSI0IR0 base_addr * MSI0IR1 base_addr + 0x10000 * ... ... * MSI0IR6 base_addr + 0x60000 * MSI0IR7 base_addr + 0x70000 * MSI1IR0 base_addr + 0x80000 * MSI1IR1 base_addr + 0x90000 * ... ... * MSI1IR7 base_addr + 0xF0000 * MSI2IR0 base_addr + 0x100000 * ... ... * MSIFIR0 base_addr + 0x780000 * MSIFIR1 base_addr + 0x790000 * ... ... * MSIFIR7 base_addr + 0x7F0000 * MSIINT0 base_addr + 0x800000 * MSIINT1 base_addr + 0x810000 * ... ... * MSIINTF base_addr + 0x8F0000 * * Each index register supports 16 MSI vectors (0..15) to generate interrupt. * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination * registers. * * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate * the MSI pending status caused by 1 of its 8 index registers. */ /* MSInIRx read helper */ static u32 xgene_msi_ir_read(struct xgene_msi *msi, u32 msi_grp, u32 msir_idx) { … } /* MSIINTn read helper */ static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) { … } /* * With 2048 MSI vectors supported, the MSI message can be constructed using * following scheme: * - Divide into 8 256-vector groups * Group 0: 0-255 * Group 1: 256-511 * Group 2: 512-767 * ... * Group 7: 1792-2047 * - Each 256-vector group is divided into 16 16-vector groups * As an example: 16 16-vector groups for 256-vector group 0-255 is * Group 0: 0-15 * Group 1: 16-32 * ... * Group 15: 240-255 * - The termination address of MSI vector in 256-vector group n and 16-vector * group x is the address of MSIxIRn * - The data for MSI vector in 16-vector group x is x */ static u32 hwirq_to_reg_set(unsigned long hwirq) { … } static u32 hwirq_to_group(unsigned long hwirq) { … } static u32 hwirq_to_msi_data(unsigned long hwirq) { … } static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { … } /* * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain * the expected behaviour of .set_affinity for each MSI interrupt, the 16 * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs * for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a * consequence, the total MSI vectors that X-Gene v1 supports will be * reduced to 256 (2048/8) vectors. */ static int hwirq_to_cpu(unsigned long hwirq) { … } static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) { … } static int xgene_msi_set_affinity(struct irq_data *irqdata, const struct cpumask *mask, bool force) { … } static struct irq_chip xgene_msi_bottom_irq_chip = …; static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { … } static void xgene_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { … } static const struct irq_domain_ops msi_domain_ops = …; static int xgene_allocate_domains(struct xgene_msi *msi) { … } static void xgene_free_domains(struct xgene_msi *msi) { … } static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) { … } static void xgene_msi_isr(struct irq_desc *desc) { … } static enum cpuhp_state pci_xgene_online; static void xgene_msi_remove(struct platform_device *pdev) { … } static int xgene_msi_hwirq_alloc(unsigned int cpu) { … } static int xgene_msi_hwirq_free(unsigned int cpu) { … } static const struct of_device_id xgene_msi_match_table[] = …; static int xgene_msi_probe(struct platform_device *pdev) { … } static struct platform_driver xgene_msi_driver = …; static int __init xgene_pcie_msi_init(void) { … } subsys_initcall(xgene_pcie_msi_init);
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