// SPDX-License-Identifier: GPL-2.0+ /* * PCIe host controller driver for NWL PCIe Bridge * Based on pcie-xilinx.c, pci-tegra.c * * (C) Copyright 2014 - 2015, Xilinx, Inc. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/msi.h> #include <linux/of_address.h> #include <linux/of_pci.h> #include <linux/of_platform.h> #include <linux/pci.h> #include <linux/pci-ecam.h> #include <linux/platform_device.h> #include <linux/irqchip/chained_irq.h> #include "../pci.h" /* Bridge core config registers */ #define BRCFG_PCIE_RX0 … #define BRCFG_PCIE_RX1 … #define BRCFG_INTERRUPT … #define BRCFG_PCIE_RX_MSG_FILTER … /* Egress - Bridge translation registers */ #define E_BREG_CAPABILITIES … #define E_BREG_CONTROL … #define E_BREG_BASE_LO … #define E_BREG_BASE_HI … #define E_ECAM_CAPABILITIES … #define E_ECAM_CONTROL … #define E_ECAM_BASE_LO … #define E_ECAM_BASE_HI … /* Ingress - address translations */ #define I_MSII_CAPABILITIES … #define I_MSII_CONTROL … #define I_MSII_BASE_LO … #define I_MSII_BASE_HI … #define I_ISUB_CONTROL … #define SET_ISUB_CONTROL … /* Rxed msg fifo - Interrupt status registers */ #define MSGF_MISC_STATUS … #define MSGF_MISC_MASK … #define MSGF_LEG_STATUS … #define MSGF_LEG_MASK … #define MSGF_MSI_STATUS_LO … #define MSGF_MSI_STATUS_HI … #define MSGF_MSI_MASK_LO … #define MSGF_MSI_MASK_HI … /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD … #define CFG_ENABLE_INT_MSG_FWD … #define CFG_ENABLE_ERR_MSG_FWD … #define CFG_ENABLE_MSG_FILTER_MASK … /* Misc interrupt status mask bits */ #define MSGF_MISC_SR_RXMSG_AVAIL … #define MSGF_MISC_SR_RXMSG_OVER … #define MSGF_MISC_SR_SLAVE_ERR … #define MSGF_MISC_SR_MASTER_ERR … #define MSGF_MISC_SR_I_ADDR_ERR … #define MSGF_MISC_SR_E_ADDR_ERR … #define MSGF_MISC_SR_FATAL_AER … #define MSGF_MISC_SR_NON_FATAL_AER … #define MSGF_MISC_SR_CORR_AER … #define MSGF_MISC_SR_UR_DETECT … #define MSGF_MISC_SR_NON_FATAL_DEV … #define MSGF_MISC_SR_FATAL_DEV … #define MSGF_MISC_SR_LINK_DOWN … #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH … #define MSGF_MSIC_SR_LINK_BWIDTH … #define MSGF_MISC_SR_MASKALL … /* Legacy interrupt status mask bits */ #define MSGF_LEG_SR_INTA … #define MSGF_LEG_SR_INTB … #define MSGF_LEG_SR_INTC … #define MSGF_LEG_SR_INTD … #define MSGF_LEG_SR_MASKALL … /* MSI interrupt status mask bits */ #define MSGF_MSI_SR_LO_MASK … #define MSGF_MSI_SR_HI_MASK … #define MSII_PRESENT … #define MSII_ENABLE … #define MSII_STATUS_ENABLE … /* Bridge config interrupt mask */ #define BRCFG_INTERRUPT_MASK … #define BREG_PRESENT … #define BREG_ENABLE … #define BREG_ENABLE_FORCE … /* E_ECAM status mask bits */ #define E_ECAM_PRESENT … #define E_ECAM_CR_ENABLE … #define E_ECAM_SIZE_LOC … #define E_ECAM_SIZE_SHIFT … #define NWL_ECAM_MAX_SIZE … #define CFG_DMA_REG_BAR … #define CFG_PCIE_CACHE … #define INT_PCI_MSI_NR … /* Readin the PS_LINKUP */ #define PS_LINKUP_OFFSET … #define PCIE_PHY_LINKUP_BIT … #define PHY_RDY_LINKUP_BIT … /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES … #define LINK_WAIT_USLEEP_MIN … #define LINK_WAIT_USLEEP_MAX … struct nwl_msi { … }; struct nwl_pcie { … }; static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) { … } static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) { … } static bool nwl_pcie_link_up(struct nwl_pcie *pcie) { … } static bool nwl_phy_link_up(struct nwl_pcie *pcie) { … } static int nwl_wait_for_link(struct nwl_pcie *pcie) { … } static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) { … } /** * nwl_pcie_map_bus - Get configuration base * * @bus: Bus structure of current bus * @devfn: Device/function * @where: Offset from base * * Return: Base address of the configuration space needed to be * accessed. */ static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { … } /* PCIe operations */ static struct pci_ops nwl_pcie_ops = …; static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) { … } static void nwl_pcie_leg_handler(struct irq_desc *desc) { … } static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) { … } static void nwl_pcie_msi_handler_high(struct irq_desc *desc) { … } static void nwl_pcie_msi_handler_low(struct irq_desc *desc) { … } static void nwl_mask_intx_irq(struct irq_data *data) { … } static void nwl_unmask_intx_irq(struct irq_data *data) { … } static struct irq_chip nwl_intx_irq_chip = …; static int nwl_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { … } static const struct irq_domain_ops intx_domain_ops = …; #ifdef CONFIG_PCI_MSI static struct irq_chip nwl_msi_irq_chip = …; static struct msi_domain_info nwl_msi_domain_info = …; #endif static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { … } static int nwl_msi_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force) { … } static struct irq_chip nwl_irq_chip = …; static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { … } static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { … } static const struct irq_domain_ops dev_msi_domain_ops = …; static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) { … } static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) { … } static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) { … } static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { … } static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, struct platform_device *pdev) { … } static const struct of_device_id nwl_pcie_of_match[] = …; static int nwl_pcie_probe(struct platform_device *pdev) { … } static struct platform_driver nwl_pcie_driver = …; builtin_platform_driver(…) …;
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