// SPDX-License-Identifier: GPL-2.0+ /* * APM X-Gene PCIe Driver * * Copyright (c) 2014 Applied Micro Circuits Corporation. * * Author: Tanmay Inamdar <[email protected]>. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/jiffies.h> #include <linux/memblock.h> #include <linux/init.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_pci.h> #include <linux/pci.h> #include <linux/pci-acpi.h> #include <linux/pci-ecam.h> #include <linux/platform_device.h> #include <linux/slab.h> #include "../pci.h" #define PCIECORE_CTLANDSTATUS … #define PIM1_1L … #define IBAR2 … #define IR2MSK … #define PIM2_1L … #define IBAR3L … #define IR3MSKL … #define PIM3_1L … #define OMR1BARL … #define OMR2BARL … #define OMR3BARL … #define CFGBARL … #define CFGBARH … #define CFGCTL … #define RTDID … #define BRIDGE_CFG_0 … #define BRIDGE_CFG_4 … #define BRIDGE_STATUS_0 … #define LINK_UP_MASK … #define AXI_EP_CFG_ACCESS … #define EN_COHERENCY … #define EN_REG … #define OB_LO_IO … #define XGENE_PCIE_DEVICEID … #define PIPE_PHY_RATE_RD(src) … #define XGENE_V1_PCI_EXP_CAP … /* PCIe IP version */ #define XGENE_PCIE_IP_VER_UNKN … #define XGENE_PCIE_IP_VER_1 … #define XGENE_PCIE_IP_VER_2 … #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) struct xgene_pcie { … }; static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg) { … } static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val) { … } static inline u32 pcie_bar_low_val(u32 addr, u32 flags) { … } static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus) { … } /* * When the address bit [17:16] is 2'b01, the Configuration access will be * treated as Type 1 and it will be forwarded to external PCIe device. */ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) { … } /* * For Configuration request, RTDID register is used as Bus Number, * Device Number and Function number of the header fields. */ static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) { … } /* * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as * the translation from PCI bus to native BUS. Entire DDR region * is mapped into PCIe space using these registers, so it can be * reached by DMA from EP devices. The BAR0/1 of bridge should be * hidden during enumeration to avoid the sizing and resource allocation * by PCIe core. */ static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) { … } static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int offset) { … } static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { … } #endif #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) static int xgene_get_csr_resource(struct acpi_device *adev, struct resource *res) { … } static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) { … } static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) { … } const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = …; static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) { … } const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = …; #endif #if defined(CONFIG_PCI_XGENE) static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr, u32 flags, u64 size) { … } static void xgene_pcie_linkup(struct xgene_pcie *port, u32 *lanes, u32 *speed) { … } static int xgene_pcie_init_port(struct xgene_pcie *port) { … } static int xgene_pcie_map_reg(struct xgene_pcie *port, struct platform_device *pdev) { … } static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port, struct resource *res, u32 offset, u64 cpu_addr, u64 pci_addr) { … } static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port) { … } static int xgene_pcie_map_ranges(struct xgene_pcie *port) { … } static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg, u64 pim, u64 size) { … } /* * X-Gene PCIe support maximum 3 inbound memory regions * This function helps to select a region based on size of region */ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) { … } static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port, struct of_pci_range *range, u8 *ib_reg_mask) { … } static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port) { … } /* clear BAR configuration which was done by firmware */ static void xgene_pcie_clear_config(struct xgene_pcie *port) { … } static int xgene_pcie_setup(struct xgene_pcie *port) { … } static struct pci_ops xgene_pcie_ops = …; static int xgene_pcie_probe(struct platform_device *pdev) { … } static const struct of_device_id xgene_pcie_match_table[] = …; static struct platform_driver xgene_pcie_driver = …; builtin_platform_driver(…) …; #endif
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