/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ /* MDIO support for Mellanox Gigabit Ethernet driver * * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES, ALL RIGHTS RESERVED. * * This software product is a proprietary product of NVIDIA CORPORATION & * AFFILIATES (the "Company") and all right, title, and interest in and to the * software product, including all associated intellectual property rights, are * and shall remain exclusively with the Company. * * This software product is governed by the End User License Agreement * provided with the software product. */ #ifndef __MLXBF_GIGE_MDIO_BF2_H__ #define __MLXBF_GIGE_MDIO_BF2_H__ #include <linux/bitfield.h> #define MLXBF2_GIGE_MDIO_GW_OFFSET … #define MLXBF2_GIGE_MDIO_CFG_OFFSET … /* MDIO GW register bits */ #define MLXBF2_GIGE_MDIO_GW_AD_MASK … #define MLXBF2_GIGE_MDIO_GW_DEVAD_MASK … #define MLXBF2_GIGE_MDIO_GW_PARTAD_MASK … #define MLXBF2_GIGE_MDIO_GW_OPCODE_MASK … #define MLXBF2_GIGE_MDIO_GW_ST1_MASK … #define MLXBF2_GIGE_MDIO_GW_BUSY_MASK … #define MLXBF2_GIGE_MDIO_GW_AD_SHIFT … #define MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT … #define MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT … #define MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT … #define MLXBF2_GIGE_MDIO_GW_ST1_SHIFT … #define MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT … /* MDIO config register bits */ #define MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK … #define MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK … #define MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK … #define MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK … #define MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK … #define MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK … #define MLXBF2_GIGE_MDIO_CFG_VAL … #endif /* __MLXBF_GIGE_MDIO_BF2_H__ */
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