// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause /* MDIO support for Mellanox Gigabit Ethernet driver * * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES */ #include <linux/acpi.h> #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/ioport.h> #include <linux/irqreturn.h> #include <linux/jiffies.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/phy.h> #include <linux/platform_device.h> #include <linux/property.h> #include "mlxbf_gige.h" #include "mlxbf_gige_regs.h" #include "mlxbf_gige_mdio_bf2.h" #include "mlxbf_gige_mdio_bf3.h" static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = …; #define MLXBF_GIGE_MDIO_FREQ_REFERENCE … #define MLXBF_GIGE_MDIO_COREPLL_CONST … #define MLXBF_GIGE_MDC_CLK_NS … #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 … #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 … #define MLXBF_GIGE_MDIO_CORE_F_SHIFT … #define MLXBF_GIGE_MDIO_CORE_F_MASK … #define MLXBF_GIGE_MDIO_CORE_R_SHIFT … #define MLXBF_GIGE_MDIO_CORE_R_MASK … #define MLXBF_GIGE_MDIO_CORE_OD_SHIFT … #define MLXBF_GIGE_MDIO_CORE_OD_MASK … /* Support clause 22 */ #define MLXBF_GIGE_MDIO_CL22_ST1 … #define MLXBF_GIGE_MDIO_CL22_WRITE … #define MLXBF_GIGE_MDIO_CL22_READ … /* Busy bit is set by software and cleared by hardware */ #define MLXBF_GIGE_MDIO_SET_BUSY … #define MLXBF_GIGE_BF2_COREPLL_ADDR … #define MLXBF_GIGE_BF2_COREPLL_SIZE … #define MLXBF_GIGE_BF3_COREPLL_ADDR … #define MLXBF_GIGE_BF3_COREPLL_SIZE … static struct resource corepll_params[] = …; /* Returns core clock i1clk in Hz */ static u64 calculate_i1clk(struct mlxbf_gige *priv) { … } /* Formula for encoding the MDIO period. The encoded value is * passed to the MDIO config register. * * mdc_clk = 2*(val + 1)*(core clock in sec) * * i1clk is in Hz: * 400 ns = 2*(val + 1)*(1/i1clk) * * val = (((400/10^9) / (1/i1clk) / 2) - 1) * val = (400/2 * i1clk)/10^9 - 1 */ static u8 mdio_period_map(struct mlxbf_gige *priv) { … } static u32 mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw *mdio_gw, u16 data, int phy_add, int phy_reg, u32 opcode) { … } static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg) { … } static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add, int phy_reg, u16 val) { … } static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv) { … } int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) { … } void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv) { … }
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