/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) */ #ifndef _LAN966X_REGS_H_ #define _LAN966X_REGS_H_ #include <linux/bitfield.h> #include <linux/types.h> #include <linux/bug.h> enum lan966x_target { … }; #define __REG(...) … /* AFI:PORT_TBL:PORT_FRM_OUT */ #define AFI_PORT_FRM_OUT(g) … #define AFI_PORT_FRM_OUT_FRM_OUT_CNT … #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x) … #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x) … /* AFI:PORT_TBL:PORT_CFG */ #define AFI_PORT_CFG(g) … #define AFI_PORT_CFG_FC_SKIP_TTI_INJ … #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x) … #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x) … #define AFI_PORT_CFG_FRM_OUT_MAX … #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x) … #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x) … /* ANA:ANA:ADVLEARN */ #define ANA_ADVLEARN … #define ANA_ADVLEARN_VLAN_CHK … #define ANA_ADVLEARN_VLAN_CHK_SET(x) … #define ANA_ADVLEARN_VLAN_CHK_GET(x) … /* ANA:ANA:VLANMASK */ #define ANA_VLANMASK … /* ANA:ANA:ANAINTR */ #define ANA_ANAINTR … #define ANA_ANAINTR_INTR … #define ANA_ANAINTR_INTR_SET(x) … #define ANA_ANAINTR_INTR_GET(x) … #define ANA_ANAINTR_INTR_ENA … #define ANA_ANAINTR_INTR_ENA_SET(x) … #define ANA_ANAINTR_INTR_ENA_GET(x) … /* ANA:ANA:AUTOAGE */ #define ANA_AUTOAGE … #define ANA_AUTOAGE_AGE_PERIOD … #define ANA_AUTOAGE_AGE_PERIOD_SET(x) … #define ANA_AUTOAGE_AGE_PERIOD_GET(x) … /* ANA:ANA:MIRRORPORTS */ #define ANA_MIRRORPORTS … #define ANA_MIRRORPORTS_MIRRORPORTS … #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x) … #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x) … /* ANA:ANA:EMIRRORPORTS */ #define ANA_EMIRRORPORTS … #define ANA_EMIRRORPORTS_EMIRRORPORTS … #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x) … #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x) … /* ANA:ANA:FLOODING */ #define ANA_FLOODING(r) … #define ANA_FLOODING_FLD_UNICAST … #define ANA_FLOODING_FLD_UNICAST_SET(x) … #define ANA_FLOODING_FLD_UNICAST_GET(x) … #define ANA_FLOODING_FLD_BROADCAST … #define ANA_FLOODING_FLD_BROADCAST_SET(x) … #define ANA_FLOODING_FLD_BROADCAST_GET(x) … #define ANA_FLOODING_FLD_MULTICAST … #define ANA_FLOODING_FLD_MULTICAST_SET(x) … #define ANA_FLOODING_FLD_MULTICAST_GET(x) … /* ANA:ANA:FLOODING_IPMC */ #define ANA_FLOODING_IPMC … #define ANA_FLOODING_IPMC_FLD_MC4_CTRL … #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x) … #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x) … #define ANA_FLOODING_IPMC_FLD_MC4_DATA … #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x) … #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x) … #define ANA_FLOODING_IPMC_FLD_MC6_CTRL … #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x) … #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x) … #define ANA_FLOODING_IPMC_FLD_MC6_DATA … #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x) … #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x) … /* ANA:PGID:PGID */ #define ANA_PGID(g) … #define ANA_PGID_PGID … #define ANA_PGID_PGID_SET(x) … #define ANA_PGID_PGID_GET(x) … /* ANA:PGID:PGID_CFG */ #define ANA_PGID_CFG(g) … #define ANA_PGID_CFG_OBEY_VLAN … #define ANA_PGID_CFG_OBEY_VLAN_SET(x) … #define ANA_PGID_CFG_OBEY_VLAN_GET(x) … /* ANA:ANA_TABLES:MACHDATA */ #define ANA_MACHDATA … /* ANA:ANA_TABLES:MACLDATA */ #define ANA_MACLDATA … /* ANA:ANA_TABLES:MACACCESS */ #define ANA_MACACCESS … #define ANA_MACACCESS_CHANGE2SW … #define ANA_MACACCESS_CHANGE2SW_SET(x) … #define ANA_MACACCESS_CHANGE2SW_GET(x) … #define ANA_MACACCESS_MAC_CPU_COPY … #define ANA_MACACCESS_MAC_CPU_COPY_SET(x) … #define ANA_MACACCESS_MAC_CPU_COPY_GET(x) … #define ANA_MACACCESS_VALID … #define ANA_MACACCESS_VALID_SET(x) … #define ANA_MACACCESS_VALID_GET(x) … #define ANA_MACACCESS_ENTRYTYPE … #define ANA_MACACCESS_ENTRYTYPE_SET(x) … #define ANA_MACACCESS_ENTRYTYPE_GET(x) … #define ANA_MACACCESS_DEST_IDX … #define ANA_MACACCESS_DEST_IDX_SET(x) … #define ANA_MACACCESS_DEST_IDX_GET(x) … #define ANA_MACACCESS_MAC_TABLE_CMD … #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x) … #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x) … /* ANA:ANA_TABLES:MACTINDX */ #define ANA_MACTINDX … #define ANA_MACTINDX_BUCKET … #define ANA_MACTINDX_BUCKET_SET(x) … #define ANA_MACTINDX_BUCKET_GET(x) … #define ANA_MACTINDX_M_INDEX … #define ANA_MACTINDX_M_INDEX_SET(x) … #define ANA_MACTINDX_M_INDEX_GET(x) … /* ANA:ANA_TABLES:VLAN_PORT_MASK */ #define ANA_VLAN_PORT_MASK … #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK … #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x) … #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x) … /* ANA:ANA_TABLES:VLANACCESS */ #define ANA_VLANACCESS … #define ANA_VLANACCESS_VLAN_TBL_CMD … #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x) … #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x) … /* ANA:ANA_TABLES:VLANTIDX */ #define ANA_VLANTIDX … #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS … #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x) … #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x) … #define ANA_VLANTIDX_V_INDEX … #define ANA_VLANTIDX_V_INDEX_SET(x) … #define ANA_VLANTIDX_V_INDEX_GET(x) … /* ANA:PORT:VLAN_CFG */ #define ANA_VLAN_CFG(g) … #define ANA_VLAN_CFG_VLAN_AWARE_ENA … #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x) … #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x) … #define ANA_VLAN_CFG_VLAN_POP_CNT … #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x) … #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x) … #define ANA_VLAN_CFG_VLAN_PCP … #define ANA_VLAN_CFG_VLAN_PCP_SET(x) … #define ANA_VLAN_CFG_VLAN_PCP_GET(x) … #define ANA_VLAN_CFG_VLAN_DEI … #define ANA_VLAN_CFG_VLAN_DEI_SET(x) … #define ANA_VLAN_CFG_VLAN_DEI_GET(x) … #define ANA_VLAN_CFG_VLAN_VID … #define ANA_VLAN_CFG_VLAN_VID_SET(x) … #define ANA_VLAN_CFG_VLAN_VID_GET(x) … /* ANA:PORT:DROP_CFG */ #define ANA_DROP_CFG(g) … #define ANA_DROP_CFG_DROP_UNTAGGED_ENA … #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x) … #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x) … #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA … #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x) … #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x) … #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA … #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x) … #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x) … #define ANA_DROP_CFG_DROP_MC_SMAC_ENA … #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x) … #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x) … /* ANA:PORT:QOS_CFG */ #define ANA_QOS_CFG(g) … #define ANA_QOS_CFG_DP_DEFAULT_VAL … #define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x) … #define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x) … #define ANA_QOS_CFG_QOS_DEFAULT_VAL … #define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x) … #define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x) … #define ANA_QOS_CFG_QOS_DSCP_ENA … #define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x) … #define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x) … #define ANA_QOS_CFG_QOS_PCP_ENA … #define ANA_QOS_CFG_QOS_PCP_ENA_SET(x) … #define ANA_QOS_CFG_QOS_PCP_ENA_GET(x) … #define ANA_QOS_CFG_DSCP_REWR_CFG … #define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x) … #define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x) … /* ANA:PORT:VCAP_CFG */ #define ANA_VCAP_CFG(g) … #define ANA_VCAP_CFG_S1_ENA … #define ANA_VCAP_CFG_S1_ENA_SET(x) … #define ANA_VCAP_CFG_S1_ENA_GET(x) … /* ANA:PORT:VCAP_S1_KEY_CFG */ #define ANA_VCAP_S1_CFG(g, r) … #define ANA_VCAP_S1_CFG_KEY_RT_CFG … #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x) … #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x) … #define ANA_VCAP_S1_CFG_KEY_IP6_CFG … #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x) … #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x) … #define ANA_VCAP_S1_CFG_KEY_IP4_CFG … #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x) … #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x) … #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG … #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x) … #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x) … /* ANA:PORT:VCAP_S2_CFG */ #define ANA_VCAP_S2_CFG(g) … #define ANA_VCAP_S2_CFG_ISDX_ENA … #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x) … #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x) … #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA … #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x) … #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x) … #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA … #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x) … #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x) … #define ANA_VCAP_S2_CFG_ENA … #define ANA_VCAP_S2_CFG_ENA_SET(x) … #define ANA_VCAP_S2_CFG_ENA_GET(x) … #define ANA_VCAP_S2_CFG_SNAP_DIS … #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x) … #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x) … #define ANA_VCAP_S2_CFG_ARP_DIS … #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x) … #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x) … #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS … #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x) … #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x) … #define ANA_VCAP_S2_CFG_IP_OTHER_DIS … #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x) … #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x) … #define ANA_VCAP_S2_CFG_IP6_CFG … #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x) … #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x) … #define ANA_VCAP_S2_CFG_OAM_DIS … #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x) … #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x) … /* ANA:PORT:QOS_PCP_DEI_MAP_CFG */ #define ANA_PCP_DEI_CFG(g, r) … #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL … #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x) … #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x) … #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL … #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x) … #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x) … /* ANA:PORT:CPU_FWD_CFG */ #define ANA_CPU_FWD_CFG(g) … #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA … #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x) … #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x) … #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA … #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x) … #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x) … #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA … #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x) … #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x) … #define ANA_CPU_FWD_CFG_SRC_COPY_ENA … #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x) … #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x) … /* ANA:PORT:CPU_FWD_BPDU_CFG */ #define ANA_CPU_FWD_BPDU_CFG(g) … /* ANA:PORT:PORT_CFG */ #define ANA_PORT_CFG(g) … #define ANA_PORT_CFG_SRC_MIRROR_ENA … #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x) … #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x) … #define ANA_PORT_CFG_LEARNAUTO … #define ANA_PORT_CFG_LEARNAUTO_SET(x) … #define ANA_PORT_CFG_LEARNAUTO_GET(x) … #define ANA_PORT_CFG_LEARN_ENA … #define ANA_PORT_CFG_LEARN_ENA_SET(x) … #define ANA_PORT_CFG_LEARN_ENA_GET(x) … #define ANA_PORT_CFG_RECV_ENA … #define ANA_PORT_CFG_RECV_ENA_SET(x) … #define ANA_PORT_CFG_RECV_ENA_GET(x) … #define ANA_PORT_CFG_PORTID_VAL … #define ANA_PORT_CFG_PORTID_VAL_SET(x) … #define ANA_PORT_CFG_PORTID_VAL_GET(x) … /* ANA:COMMON:DSCP_REWR_CFG */ #define ANA_DSCP_REWR_CFG(r) … #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL … #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x) … #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x) … /* ANA:PORT:POL_CFG */ #define ANA_POL_CFG(g) … #define ANA_POL_CFG_PORT_POL_ENA … #define ANA_POL_CFG_PORT_POL_ENA_SET(x) … #define ANA_POL_CFG_PORT_POL_ENA_GET(x) … #define ANA_POL_CFG_POL_ORDER … #define ANA_POL_CFG_POL_ORDER_SET(x) … #define ANA_POL_CFG_POL_ORDER_GET(x) … /* ANA:PFC:PFC_CFG */ #define ANA_PFC_CFG(g) … #define ANA_PFC_CFG_FC_LINK_SPEED … #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x) … #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x) … /* ANA:COMMON:AGGR_CFG */ #define ANA_AGGR_CFG … #define ANA_AGGR_CFG_AC_RND_ENA … #define ANA_AGGR_CFG_AC_RND_ENA_SET(x) … #define ANA_AGGR_CFG_AC_RND_ENA_GET(x) … #define ANA_AGGR_CFG_AC_DMAC_ENA … #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x) … #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x) … #define ANA_AGGR_CFG_AC_SMAC_ENA … #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x) … #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x) … #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA … #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x) … #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x) … #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA … #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x) … #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x) … #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA … #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x) … #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x) … #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA … #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x) … #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x) … /* ANA:COMMON:DSCP_CFG */ #define ANA_DSCP_CFG(r) … #define ANA_DSCP_CFG_DP_DSCP_VAL … #define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x) … #define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x) … #define ANA_DSCP_CFG_QOS_DSCP_VAL … #define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x) … #define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x) … #define ANA_DSCP_CFG_DSCP_TRUST_ENA … #define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x) … #define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x) … #define ANA_DSCP_CFG_DSCP_REWR_ENA … #define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x) … #define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x) … /* ANA:POL:POL_PIR_CFG */ #define ANA_POL_PIR_CFG(g) … #define ANA_POL_PIR_CFG_PIR_RATE … #define ANA_POL_PIR_CFG_PIR_RATE_SET(x) … #define ANA_POL_PIR_CFG_PIR_RATE_GET(x) … #define ANA_POL_PIR_CFG_PIR_BURST … #define ANA_POL_PIR_CFG_PIR_BURST_SET(x) … #define ANA_POL_PIR_CFG_PIR_BURST_GET(x) … /* ANA:POL:POL_MODE_CFG */ #define ANA_POL_MODE(g) … #define ANA_POL_MODE_DROP_ON_YELLOW_ENA … #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x) … #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x) … #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA … #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x) … #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x) … #define ANA_POL_MODE_IPG_SIZE … #define ANA_POL_MODE_IPG_SIZE_SET(x) … #define ANA_POL_MODE_IPG_SIZE_GET(x) … #define ANA_POL_MODE_FRM_MODE … #define ANA_POL_MODE_FRM_MODE_SET(x) … #define ANA_POL_MODE_FRM_MODE_GET(x) … #define ANA_POL_MODE_OVERSHOOT_ENA … #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x) … #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x) … /* ANA:POL:POL_PIR_STATE */ #define ANA_POL_PIR_STATE(g) … #define ANA_POL_PIR_STATE_PIR_LVL … #define ANA_POL_PIR_STATE_PIR_LVL_SET(x) … #define ANA_POL_PIR_STATE_PIR_LVL_GET(x) … /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ #define CHIP_TOP_CUPHY_PORT_CFG(r) … #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA … #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x) … #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x) … /* DEV:PORT_MODE:CLOCK_CFG */ #define DEV_CLOCK_CFG(t) … #define DEV_CLOCK_CFG_MAC_TX_RST … #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x) … #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x) … #define DEV_CLOCK_CFG_MAC_RX_RST … #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x) … #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x) … #define DEV_CLOCK_CFG_PCS_TX_RST … #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x) … #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x) … #define DEV_CLOCK_CFG_PCS_RX_RST … #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x) … #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x) … #define DEV_CLOCK_CFG_PORT_RST … #define DEV_CLOCK_CFG_PORT_RST_SET(x) … #define DEV_CLOCK_CFG_PORT_RST_GET(x) … #define DEV_CLOCK_CFG_LINK_SPEED … #define DEV_CLOCK_CFG_LINK_SPEED_SET(x) … #define DEV_CLOCK_CFG_LINK_SPEED_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV_MAC_ENA_CFG(t) … #define DEV_MAC_ENA_CFG_RX_ENA … #define DEV_MAC_ENA_CFG_RX_ENA_SET(x) … #define DEV_MAC_ENA_CFG_RX_ENA_GET(x) … #define DEV_MAC_ENA_CFG_TX_ENA … #define DEV_MAC_ENA_CFG_TX_ENA_SET(x) … #define DEV_MAC_ENA_CFG_TX_ENA_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ #define DEV_MAC_MODE_CFG(t) … #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA … #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x) … #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ #define DEV_MAC_MAXLEN_CFG(t) … #define DEV_MAC_MAXLEN_CFG_MAX_LEN … #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x) … #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */ #define DEV_MAC_TAGS_CFG(t) … #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA … #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x) … #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x) … #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA … #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x) … #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ #define DEV_MAC_IFG_CFG(t) … #define DEV_MAC_IFG_CFG_TX_IFG … #define DEV_MAC_IFG_CFG_TX_IFG_SET(x) … #define DEV_MAC_IFG_CFG_TX_IFG_GET(x) … #define DEV_MAC_IFG_CFG_RX_IFG2 … #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x) … #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x) … #define DEV_MAC_IFG_CFG_RX_IFG1 … #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x) … #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ #define DEV_MAC_HDX_CFG(t) … #define DEV_MAC_HDX_CFG_SEED … #define DEV_MAC_HDX_CFG_SEED_SET(x) … #define DEV_MAC_HDX_CFG_SEED_GET(x) … #define DEV_MAC_HDX_CFG_SEED_LOAD … #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x) … #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x) … /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ #define DEV_FC_MAC_LOW_CFG(t) … /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ #define DEV_FC_MAC_HIGH_CFG(t) … /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ #define DEV_PCS1G_CFG(t) … #define DEV_PCS1G_CFG_PCS_ENA … #define DEV_PCS1G_CFG_PCS_ENA_SET(x) … #define DEV_PCS1G_CFG_PCS_ENA_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ #define DEV_PCS1G_MODE_CFG(t) … #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA … #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x) … #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x) … #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA … #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x) … #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ #define DEV_PCS1G_SD_CFG(t) … #define DEV_PCS1G_SD_CFG_SD_ENA … #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x) … #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ #define DEV_PCS1G_ANEG_CFG(t) … #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY … #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x) … #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x) … #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA … #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x) … #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x) … #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT … #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x) … #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x) … #define DEV_PCS1G_ANEG_CFG_ENA … #define DEV_PCS1G_ANEG_CFG_ENA_SET(x) … #define DEV_PCS1G_ANEG_CFG_ENA_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ #define DEV_PCS1G_ANEG_STATUS(t) … #define DEV_PCS1G_ANEG_STATUS_LP_ADV … #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x) … #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x) … #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE … #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x) … #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ #define DEV_PCS1G_LINK_STATUS(t) … #define DEV_PCS1G_LINK_STATUS_LINK_STATUS … #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x) … #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x) … #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS … #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x) … #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x) … /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ #define DEV_PCS1G_STICKY(t) … #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY … #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x) … #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x) … /* FDMA:FDMA:FDMA_CH_ACTIVATE */ #define FDMA_CH_ACTIVATE … #define FDMA_CH_ACTIVATE_CH_ACTIVATE … #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x) … #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x) … /* FDMA:FDMA:FDMA_CH_RELOAD */ #define FDMA_CH_RELOAD … #define FDMA_CH_RELOAD_CH_RELOAD … #define FDMA_CH_RELOAD_CH_RELOAD_SET(x) … #define FDMA_CH_RELOAD_CH_RELOAD_GET(x) … /* FDMA:FDMA:FDMA_CH_DISABLE */ #define FDMA_CH_DISABLE … #define FDMA_CH_DISABLE_CH_DISABLE … #define FDMA_CH_DISABLE_CH_DISABLE_SET(x) … #define FDMA_CH_DISABLE_CH_DISABLE_GET(x) … /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ #define FDMA_CH_DB_DISCARD … #define FDMA_CH_DB_DISCARD_DB_DISCARD … #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x) … #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x) … /* FDMA:FDMA:FDMA_DCB_LLP */ #define FDMA_DCB_LLP(r) … /* FDMA:FDMA:FDMA_DCB_LLP1 */ #define FDMA_DCB_LLP1(r) … /* FDMA:FDMA:FDMA_CH_ACTIVE */ #define FDMA_CH_ACTIVE … /* FDMA:FDMA:FDMA_CH_CFG */ #define FDMA_CH_CFG(r) … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x) … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x) … #define FDMA_CH_CFG_CH_INJ_PORT … #define FDMA_CH_CFG_CH_INJ_PORT_SET(x) … #define FDMA_CH_CFG_CH_INJ_PORT_GET(x) … #define FDMA_CH_CFG_CH_DCB_DB_CNT … #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x) … #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x) … #define FDMA_CH_CFG_CH_MEM … #define FDMA_CH_CFG_CH_MEM_SET(x) … #define FDMA_CH_CFG_CH_MEM_GET(x) … /* FDMA:FDMA:FDMA_PORT_CTRL */ #define FDMA_PORT_CTRL(r) … #define FDMA_PORT_CTRL_INJ_STOP … #define FDMA_PORT_CTRL_INJ_STOP_SET(x) … #define FDMA_PORT_CTRL_INJ_STOP_GET(x) … #define FDMA_PORT_CTRL_XTR_STOP … #define FDMA_PORT_CTRL_XTR_STOP_SET(x) … #define FDMA_PORT_CTRL_XTR_STOP_GET(x) … /* FDMA:FDMA:FDMA_INTR_DB */ #define FDMA_INTR_DB … /* FDMA:FDMA:FDMA_INTR_DB_ENA */ #define FDMA_INTR_DB_ENA … #define FDMA_INTR_DB_ENA_INTR_DB_ENA … #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x) … #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x) … /* FDMA:FDMA:FDMA_INTR_ERR */ #define FDMA_INTR_ERR … /* FDMA:FDMA:FDMA_ERRORS */ #define FDMA_ERRORS … /* PTP:PTP_CFG:PTP_PIN_INTR */ #define PTP_PIN_INTR … #define PTP_PIN_INTR_INTR_PTP … #define PTP_PIN_INTR_INTR_PTP_SET(x) … #define PTP_PIN_INTR_INTR_PTP_GET(x) … /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ #define PTP_PIN_INTR_ENA … #define PTP_PIN_INTR_ENA_INTR_ENA … #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x) … #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x) … /* PTP:PTP_CFG:PTP_DOM_CFG */ #define PTP_DOM_CFG … #define PTP_DOM_CFG_ENA … #define PTP_DOM_CFG_ENA_SET(x) … #define PTP_DOM_CFG_ENA_GET(x) … #define PTP_DOM_CFG_CLKCFG_DIS … #define PTP_DOM_CFG_CLKCFG_DIS_SET(x) … #define PTP_DOM_CFG_CLKCFG_DIS_GET(x) … /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ #define PTP_CLK_PER_CFG(g, r) … /* PTP:PTP_PINS:PTP_PIN_CFG */ #define PTP_PIN_CFG(g) … #define PTP_PIN_CFG_PIN_ACTION … #define PTP_PIN_CFG_PIN_ACTION_SET(x) … #define PTP_PIN_CFG_PIN_ACTION_GET(x) … #define PTP_PIN_CFG_PIN_SYNC … #define PTP_PIN_CFG_PIN_SYNC_SET(x) … #define PTP_PIN_CFG_PIN_SYNC_GET(x) … #define PTP_PIN_CFG_PIN_SELECT … #define PTP_PIN_CFG_PIN_SELECT_SET(x) … #define PTP_PIN_CFG_PIN_SELECT_GET(x) … #define PTP_PIN_CFG_PIN_DOM … #define PTP_PIN_CFG_PIN_DOM_SET(x) … #define PTP_PIN_CFG_PIN_DOM_GET(x) … /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ #define PTP_TOD_SEC_MSB(g) … #define PTP_TOD_SEC_MSB_TOD_SEC_MSB … #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x) … #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x) … /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ #define PTP_TOD_SEC_LSB(g) … /* PTP:PTP_PINS:PTP_TOD_NSEC */ #define PTP_TOD_NSEC(g) … #define PTP_TOD_NSEC_TOD_NSEC … #define PTP_TOD_NSEC_TOD_NSEC_SET(x) … #define PTP_TOD_NSEC_TOD_NSEC_GET(x) … /* PTP:PTP_PINS:WF_HIGH_PERIOD */ #define PTP_WF_HIGH_PERIOD(g) … #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) … #define PTP_WF_HIGH_PERIOD_PIN_WFH_M … #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) … /* PTP:PTP_PINS:WF_LOW_PERIOD */ #define PTP_WF_LOW_PERIOD(g) … #define PTP_WF_LOW_PERIOD_PIN_WFL(x) … #define PTP_WF_LOW_PERIOD_PIN_WFL_M … #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) … /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ #define PTP_TWOSTEP_CTRL … #define PTP_TWOSTEP_CTRL_NXT … #define PTP_TWOSTEP_CTRL_NXT_SET(x) … #define PTP_TWOSTEP_CTRL_NXT_GET(x) … #define PTP_TWOSTEP_CTRL_VLD … #define PTP_TWOSTEP_CTRL_VLD_SET(x) … #define PTP_TWOSTEP_CTRL_VLD_GET(x) … #define PTP_TWOSTEP_CTRL_STAMP_TX … #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x) … #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x) … #define PTP_TWOSTEP_CTRL_STAMP_PORT … #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x) … #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x) … #define PTP_TWOSTEP_CTRL_OVFL … #define PTP_TWOSTEP_CTRL_OVFL_SET(x) … #define PTP_TWOSTEP_CTRL_OVFL_GET(x) … /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ #define PTP_TWOSTEP_STAMP … #define PTP_TWOSTEP_STAMP_STAMP_NSEC … #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x) … #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x) … /* DEVCPU_QS:XTR:XTR_GRP_CFG */ #define QS_XTR_GRP_CFG(r) … #define QS_XTR_GRP_CFG_MODE … #define QS_XTR_GRP_CFG_MODE_SET(x) … #define QS_XTR_GRP_CFG_MODE_GET(x) … #define QS_XTR_GRP_CFG_BYTE_SWAP … #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x) … #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x) … /* DEVCPU_QS:XTR:XTR_RD */ #define QS_XTR_RD(r) … /* DEVCPU_QS:XTR:XTR_FLUSH */ #define QS_XTR_FLUSH … /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ #define QS_XTR_DATA_PRESENT … /* DEVCPU_QS:INJ:INJ_GRP_CFG */ #define QS_INJ_GRP_CFG(r) … #define QS_INJ_GRP_CFG_MODE … #define QS_INJ_GRP_CFG_MODE_SET(x) … #define QS_INJ_GRP_CFG_MODE_GET(x) … #define QS_INJ_GRP_CFG_BYTE_SWAP … #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x) … #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x) … /* DEVCPU_QS:INJ:INJ_WR */ #define QS_INJ_WR(r) … /* DEVCPU_QS:INJ:INJ_CTRL */ #define QS_INJ_CTRL(r) … #define QS_INJ_CTRL_GAP_SIZE … #define QS_INJ_CTRL_GAP_SIZE_SET(x) … #define QS_INJ_CTRL_GAP_SIZE_GET(x) … #define QS_INJ_CTRL_EOF … #define QS_INJ_CTRL_EOF_SET(x) … #define QS_INJ_CTRL_EOF_GET(x) … #define QS_INJ_CTRL_SOF … #define QS_INJ_CTRL_SOF_SET(x) … #define QS_INJ_CTRL_SOF_GET(x) … #define QS_INJ_CTRL_VLD_BYTES … #define QS_INJ_CTRL_VLD_BYTES_SET(x) … #define QS_INJ_CTRL_VLD_BYTES_GET(x) … /* DEVCPU_QS:INJ:INJ_STATUS */ #define QS_INJ_STATUS … #define QS_INJ_STATUS_WMARK_REACHED … #define QS_INJ_STATUS_WMARK_REACHED_SET(x) … #define QS_INJ_STATUS_WMARK_REACHED_GET(x) … #define QS_INJ_STATUS_FIFO_RDY … #define QS_INJ_STATUS_FIFO_RDY_SET(x) … #define QS_INJ_STATUS_FIFO_RDY_GET(x) … /* QSYS:SYSTEM:PORT_MODE */ #define QSYS_PORT_MODE(r) … #define QSYS_PORT_MODE_DEQUEUE_DIS … #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x) … #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x) … /* QSYS:SYSTEM:SWITCH_PORT_MODE */ #define QSYS_SW_PORT_MODE(r) … #define QSYS_SW_PORT_MODE_PORT_ENA … #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x) … #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x) … #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG … #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x) … #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x) … #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE … #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x) … #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x) … #define QSYS_SW_PORT_MODE_TX_PFC_ENA … #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x) … #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x) … #define QSYS_SW_PORT_MODE_AGING_MODE … #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x) … #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x) … /* QSYS:SYSTEM:SW_STATUS */ #define QSYS_SW_STATUS(r) … #define QSYS_SW_STATUS_EQ_AVAIL … #define QSYS_SW_STATUS_EQ_AVAIL_SET(x) … #define QSYS_SW_STATUS_EQ_AVAIL_GET(x) … /* QSYS:SYSTEM:CPU_GROUP_MAP */ #define QSYS_CPU_GROUP_MAP … /* QSYS:RES_CTRL:RES_CFG */ #define QSYS_RES_CFG(g) … /* QSYS:HSCH:CIR_CFG */ #define QSYS_CIR_CFG(g) … #define QSYS_CIR_CFG_CIR_RATE … #define QSYS_CIR_CFG_CIR_RATE_SET(x) … #define QSYS_CIR_CFG_CIR_RATE_GET(x) … #define QSYS_CIR_CFG_CIR_BURST … #define QSYS_CIR_CFG_CIR_BURST_SET(x) … #define QSYS_CIR_CFG_CIR_BURST_GET(x) … /* QSYS:HSCH:SE_CFG */ #define QSYS_SE_CFG(g) … #define QSYS_SE_CFG_SE_DWRR_CNT … #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x) … #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x) … #define QSYS_SE_CFG_SE_RR_ENA … #define QSYS_SE_CFG_SE_RR_ENA_SET(x) … #define QSYS_SE_CFG_SE_RR_ENA_GET(x) … #define QSYS_SE_CFG_SE_AVB_ENA … #define QSYS_SE_CFG_SE_AVB_ENA_SET(x) … #define QSYS_SE_CFG_SE_AVB_ENA_GET(x) … #define QSYS_SE_CFG_SE_FRM_MODE … #define QSYS_SE_CFG_SE_FRM_MODE_SET(x) … #define QSYS_SE_CFG_SE_FRM_MODE_GET(x) … #define QSYS_SE_DWRR_CFG(g, r) … #define QSYS_SE_DWRR_CFG_DWRR_COST … #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x) … #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x) … /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ #define QSYS_TAS_CFG_CTRL … #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX … #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x) … #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x) … #define QSYS_TAS_CFG_CTRL_LIST_NUM … #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x) … #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x) … #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q … #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x) … #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x) … #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM … #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x) … #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x) … /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ #define QSYS_TAS_GS_CTRL … #define QSYS_TAS_GS_CTRL_HSCH_POS … #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x) … #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x) … /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ #define QSYS_TAS_STM_CFG … #define QSYS_TAS_STM_CFG_REVISIT_DLY … #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x) … #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x) … /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ #define QSYS_TAS_PROFILE_CFG(g) … #define QSYS_TAS_PROFILE_CFG_PORT_NUM … #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x) … #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x) … #define QSYS_TAS_PROFILE_CFG_LINK_SPEED … #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x) … #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x) … /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ #define QSYS_TAS_BT_NSEC … #define QSYS_TAS_BT_NSEC_NSEC … #define QSYS_TAS_BT_NSEC_NSEC_SET(x) … #define QSYS_TAS_BT_NSEC_NSEC_GET(x) … /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ #define QSYS_TAS_BT_SEC_LSB … /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ #define QSYS_TAS_BT_SEC_MSB … #define QSYS_TAS_BT_SEC_MSB_SEC_MSB … #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x) … #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x) … /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ #define QSYS_TAS_CT_CFG … /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ #define QSYS_TAS_STARTUP_CFG … #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX … #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x) … #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x) … /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ #define QSYS_TAS_LIST_CFG … #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR … #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x) … #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x) … /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ #define QSYS_TAS_LST … #define QSYS_TAS_LST_LIST_STATE … #define QSYS_TAS_LST_LIST_STATE_SET(x) … #define QSYS_TAS_LST_LIST_STATE_GET(x) … /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ #define QSYS_TAS_GCL_CT_CFG … #define QSYS_TAS_GCL_CT_CFG_HSCH_POS … #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x) … #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x) … #define QSYS_TAS_GCL_CT_CFG_GATE_STATE … #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x) … #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x) … #define QSYS_TAS_GCL_CT_CFG_OP_TYPE … #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x) … #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x) … /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ #define QSYS_TAS_GCL_CT_CFG2 … #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE … #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x) … #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x) … #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL … #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x) … #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x) … /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ #define QSYS_TAS_GCL_TM_CFG … /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ #define QSYS_TAS_GATE_STATE … #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE … #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x) … #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x) … /* REW:PORT:PORT_VLAN_CFG */ #define REW_PORT_VLAN_CFG(g) … #define REW_PORT_VLAN_CFG_PORT_TPID … #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x) … #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x) … #define REW_PORT_VLAN_CFG_PORT_VID … #define REW_PORT_VLAN_CFG_PORT_VID_SET(x) … #define REW_PORT_VLAN_CFG_PORT_VID_GET(x) … /* REW:PORT:TAG_CFG */ #define REW_TAG_CFG(g) … #define REW_TAG_CFG_TAG_CFG … #define REW_TAG_CFG_TAG_CFG_SET(x) … #define REW_TAG_CFG_TAG_CFG_GET(x) … #define REW_TAG_CFG_TAG_TPID_CFG … #define REW_TAG_CFG_TAG_TPID_CFG_SET(x) … #define REW_TAG_CFG_TAG_TPID_CFG_GET(x) … #define REW_TAG_CFG_TAG_PCP_CFG … #define REW_TAG_CFG_TAG_PCP_CFG_SET(x) … #define REW_TAG_CFG_TAG_PCP_CFG_GET(x) … #define REW_TAG_CFG_TAG_DEI_CFG … #define REW_TAG_CFG_TAG_DEI_CFG_SET(x) … #define REW_TAG_CFG_TAG_DEI_CFG_GET(x) … /* REW:PORT:PORT_CFG */ #define REW_PORT_CFG(g) … #define REW_PORT_CFG_ES0_EN … #define REW_PORT_CFG_ES0_EN_SET(x) … #define REW_PORT_CFG_ES0_EN_GET(x) … #define REW_PORT_CFG_NO_REWRITE … #define REW_PORT_CFG_NO_REWRITE_SET(x) … #define REW_PORT_CFG_NO_REWRITE_GET(x) … /* REW:PORT:DSCP_CFG */ #define REW_DSCP_CFG(g) … #define REW_DSCP_CFG_DSCP_REWR_CFG … #define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x) … #define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x) … /* REW:PORT:PCP_DEI_QOS_MAP_CFG */ #define REW_PCP_DEI_CFG(g, r) … #define REW_PCP_DEI_CFG_DEI_QOS_VAL … #define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x) … #define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x) … #define REW_PCP_DEI_CFG_PCP_QOS_VAL … #define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x) … #define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x) … /* REW:COMMON:STAT_CFG */ #define REW_STAT_CFG … #define REW_STAT_CFG_STAT_MODE … #define REW_STAT_CFG_STAT_MODE_SET(x) … #define REW_STAT_CFG_STAT_MODE_GET(x) … /* SYS:SYSTEM:RESET_CFG */ #define SYS_RESET_CFG … #define SYS_RESET_CFG_CORE_ENA … #define SYS_RESET_CFG_CORE_ENA_SET(x) … #define SYS_RESET_CFG_CORE_ENA_GET(x) … /* SYS:SYSTEM:PORT_MODE */ #define SYS_PORT_MODE(r) … #define SYS_PORT_MODE_INCL_INJ_HDR … #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x) … #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x) … #define SYS_PORT_MODE_INCL_XTR_HDR … #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x) … #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x) … /* SYS:SYSTEM:FRONT_PORT_MODE */ #define SYS_FRONT_PORT_MODE(r) … #define SYS_FRONT_PORT_MODE_HDX_MODE … #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x) … #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x) … /* SYS:SYSTEM:FRM_AGING */ #define SYS_FRM_AGING … #define SYS_FRM_AGING_AGE_TX_ENA … #define SYS_FRM_AGING_AGE_TX_ENA_SET(x) … #define SYS_FRM_AGING_AGE_TX_ENA_GET(x) … /* SYS:SYSTEM:STAT_CFG */ #define SYS_STAT_CFG … #define SYS_STAT_CFG_STAT_VIEW … #define SYS_STAT_CFG_STAT_VIEW_SET(x) … #define SYS_STAT_CFG_STAT_VIEW_GET(x) … /* SYS:PAUSE_CFG:PAUSE_CFG */ #define SYS_PAUSE_CFG(r) … #define SYS_PAUSE_CFG_PAUSE_START … #define SYS_PAUSE_CFG_PAUSE_START_SET(x) … #define SYS_PAUSE_CFG_PAUSE_START_GET(x) … #define SYS_PAUSE_CFG_PAUSE_STOP … #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x) … #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x) … #define SYS_PAUSE_CFG_PAUSE_ENA … #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x) … #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x) … /* SYS:PAUSE_CFG:ATOP */ #define SYS_ATOP(r) … /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ #define SYS_ATOP_TOT_CFG … /* SYS:PAUSE_CFG:MAC_FC_CFG */ #define SYS_MAC_FC_CFG(r) … #define SYS_MAC_FC_CFG_FC_LINK_SPEED … #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x) … #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x) … #define SYS_MAC_FC_CFG_FC_LATENCY_CFG … #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x) … #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x) … #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA … #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x) … #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x) … #define SYS_MAC_FC_CFG_TX_FC_ENA … #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x) … #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x) … #define SYS_MAC_FC_CFG_RX_FC_ENA … #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x) … #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x) … #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG … #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x) … #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x) … /* SYS:STAT:CNT */ #define SYS_CNT(g) … /* SYS:RAM_CTRL:RAM_INIT */ #define SYS_RAM_INIT … #define SYS_RAM_INIT_RAM_INIT … #define SYS_RAM_INIT_RAM_INIT_SET(x) … #define SYS_RAM_INIT_RAM_INIT_GET(x) … /* VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ #define VCAP_UPDATE_CTRL(t) … #define VCAP_UPDATE_CTRL_UPDATE_CMD … #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS … #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS … #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x) … #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS … #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ADDR … #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x) … #define VCAP_UPDATE_CTRL_UPDATE_SHOT … #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x) … #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x) … #define VCAP_UPDATE_CTRL_CLEAR_CACHE … #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x) … #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x) … #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN … #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x) … #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x) … /* VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */ #define VCAP_MV_CFG(t) … #define VCAP_MV_CFG_MV_NUM_POS … #define VCAP_MV_CFG_MV_NUM_POS_SET(x) … #define VCAP_MV_CFG_MV_NUM_POS_GET(x) … #define VCAP_MV_CFG_MV_SIZE … #define VCAP_MV_CFG_MV_SIZE_SET(x) … #define VCAP_MV_CFG_MV_SIZE_GET(x) … /* VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ #define VCAP_ENTRY_DAT(t, r) … /* VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */ #define VCAP_MASK_DAT(t, r) … /* VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ #define VCAP_ACTION_DAT(t, r) … /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */ #define VCAP_CNT_DAT(t, r) … /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ #define VCAP_CNT_FW_DAT(t) … /* VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */ #define VCAP_TG_DAT(t) … /* VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */ #define VCAP_CORE_IDX(t) … #define VCAP_CORE_IDX_CORE_IDX … #define VCAP_CORE_IDX_CORE_IDX_SET(x) … #define VCAP_CORE_IDX_CORE_IDX_GET(x) … /* VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */ #define VCAP_CORE_MAP(t) … #define VCAP_CORE_MAP_CORE_MAP … #define VCAP_CORE_MAP_CORE_MAP_SET(x) … #define VCAP_CORE_MAP_CORE_MAP_GET(x) … /* VCAP:VCAP_CONST:VCAP_VER */ #define VCAP_VER(t) … /* VCAP:VCAP_CONST:ENTRY_WIDTH */ #define VCAP_ENTRY_WIDTH(t) … /* VCAP:VCAP_CONST:ENTRY_CNT */ #define VCAP_ENTRY_CNT(t) … /* VCAP:VCAP_CONST:ENTRY_SWCNT */ #define VCAP_ENTRY_SWCNT(t) … /* VCAP:VCAP_CONST:ENTRY_TG_WIDTH */ #define VCAP_ENTRY_TG_WIDTH(t) … /* VCAP:VCAP_CONST:ACTION_DEF_CNT */ #define VCAP_ACTION_DEF_CNT(t) … /* VCAP:VCAP_CONST:ACTION_WIDTH */ #define VCAP_ACTION_WIDTH(t) … /* VCAP:VCAP_CONST:CNT_WIDTH */ #define VCAP_CNT_WIDTH(t) … /* VCAP:VCAP_CONST:CORE_CNT */ #define VCAP_CORE_CNT(t) … /* VCAP:VCAP_CONST:IF_CNT */ #define VCAP_IF_CNT(t) … #endif /* _LAN966X_REGS_H_ */
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