/* SPDX-License-Identifier: GPL-2.0+ * Microchip Sparx5 Switch driver * * Copyright (c) 2021 Microchip Technology Inc. */ /* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100. * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada */ #ifndef _SPARX5_MAIN_REGS_H_ #define _SPARX5_MAIN_REGS_H_ #include <linux/bitfield.h> #include <linux/types.h> #include <linux/bug.h> enum sparx5_target { … }; #define __REG(...) … /* ANA_AC:RAM_CTRL:RAM_INIT */ #define ANA_AC_RAM_INIT … #define ANA_AC_RAM_INIT_RAM_INIT … #define ANA_AC_RAM_INIT_RAM_INIT_SET(x) … #define ANA_AC_RAM_INIT_RAM_INIT_GET(x) … #define ANA_AC_RAM_INIT_RAM_CFG_HOOK … #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* ANA_AC:PS_COMMON:OWN_UPSID */ #define ANA_AC_OWN_UPSID(r) … #define ANA_AC_OWN_UPSID_OWN_UPSID … #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x) … #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x) … /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ #define ANA_AC_PROBE_CFG(g) … #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD … #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x) … #define ANA_AC_PROBE_CFG_PROBE_CPU_SET … #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x) … #define ANA_AC_PROBE_CFG_PROBE_VID … #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x) … #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE … #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x) … #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE … #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x) … #define ANA_AC_PROBE_CFG_PROBE_DIRECTION … #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x) … #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x) … /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ #define ANA_AC_PROBE_PORT_CFG(g) … /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ #define ANA_AC_PROBE_PORT_CFG1(g) … /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ #define ANA_AC_PROBE_PORT_CFG2(g) … #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 … #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x) … #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x) … /* ANA_AC:SRC:SRC_CFG */ #define ANA_AC_SRC_CFG(g) … /* ANA_AC:SRC:SRC_CFG1 */ #define ANA_AC_SRC_CFG1(g) … /* ANA_AC:SRC:SRC_CFG2 */ #define ANA_AC_SRC_CFG2(g) … #define ANA_AC_SRC_CFG2_PORT_MASK2 … #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x) … #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x) … /* ANA_AC:PGID:PGID_CFG */ #define ANA_AC_PGID_CFG(g) … /* ANA_AC:PGID:PGID_CFG1 */ #define ANA_AC_PGID_CFG1(g) … /* ANA_AC:PGID:PGID_CFG2 */ #define ANA_AC_PGID_CFG2(g) … #define ANA_AC_PGID_CFG2_PORT_MASK2 … #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x) … #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x) … /* ANA_AC:PGID:PGID_MISC_CFG */ #define ANA_AC_PGID_MISC_CFG(g) … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x) … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x) … #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA … #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x) … #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x) … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x) … #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x) … /* ANA_AC:TSN_SF:TSN_SF */ #define ANA_AC_TSN_SF … #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY … #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x) … #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x) … #define ANA_AC_TSN_SF_PORT_NUM … #define ANA_AC_TSN_SF_PORT_NUM_SET(x) … #define ANA_AC_TSN_SF_PORT_NUM_GET(x) … /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ #define ANA_AC_TSN_SF_CFG(g) … #define ANA_AC_TSN_SF_CFG_TSN_SGID … #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x) … #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x) … #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU … #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x) … #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x) … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x) … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x) … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x) … #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x) … /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ #define ANA_AC_TSN_SF_STATUS … #define ANA_AC_TSN_SF_STATUS_FRM_LEN … #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x) … #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x) … #define ANA_AC_TSN_SF_STATUS_DLB_DROP … #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x) … #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x) … #define ANA_AC_TSN_SF_STATUS_TSN_SFID … #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x) … #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x) … #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD … #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x) … #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x) … /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ #define ANA_AC_SG_ACCESS_CTRL … #define ANA_AC_SG_ACCESS_CTRL_SGID … #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x) … #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x) … #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE … #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x) … #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x) … /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x) … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x) … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x) … #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x) … /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ #define ANA_AC_SG_CONFIG_REG_1 … /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ #define ANA_AC_SG_CONFIG_REG_2 … /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ #define ANA_AC_SG_CONFIG_REG_3 … #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB … #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH … #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE … #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS … #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE … #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x) … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x) … #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x) … /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ #define ANA_AC_SG_CONFIG_REG_4 … /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ #define ANA_AC_SG_CONFIG_REG_5 … /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ #define ANA_AC_SG_GCL_GS_CONFIG(r) … #define ANA_AC_SG_GCL_GS_CONFIG_IPS … #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x) … #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x) … #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE … #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x) … #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x) … /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ #define ANA_AC_SG_GCL_TI_CONFIG(r) … /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ #define ANA_AC_SG_GCL_OCT_CONFIG(r) … /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ #define ANA_AC_SG_STATUS_REG_1 … /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ #define ANA_AC_SG_STATUS_REG_2 … /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ #define ANA_AC_SG_STATUS_REG_3 … #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB … #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x) … #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x) … #define ANA_AC_SG_STATUS_REG_3_GATE_STATE … #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x) … #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x) … #define ANA_AC_SG_STATUS_REG_3_IPS … #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x) … #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x) … #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING … #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x) … #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x) … #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX … #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x) … #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x) … /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ #define ANA_AC_SG_STATUS_REG_4 … /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ #define ANA_AC_PORT_SGE_CFG(r) … #define ANA_AC_PORT_SGE_CFG_MASK … #define ANA_AC_PORT_SGE_CFG_MASK_SET(x) … #define ANA_AC_PORT_SGE_CFG_MASK_GET(x) … /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ #define ANA_AC_STAT_RESET … #define ANA_AC_STAT_RESET_RESET … #define ANA_AC_STAT_RESET_RESET_SET(x) … #define ANA_AC_STAT_RESET_RESET_GET(x) … /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ #define ANA_AC_PORT_STAT_CFG(g, r) … #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK … #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x) … #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x) … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x) … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x) … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x) … #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x) … /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ #define ANA_AC_PORT_STAT_LSB_CNT(g, r) … /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) … #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE … #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x) … #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x) … /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) … #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE … #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x) … #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x) … /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) … #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK … #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x) … #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x) … /* ANA_ACL:COMMON:VCAP_S2_CFG */ #define ANA_ACL_VCAP_S2_CFG(r) … #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_ENA … #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x) … #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x) … /* ANA_ACL:COMMON:SWAP_IP_CTRL */ #define ANA_ACL_SWAP_IP_CTRL … #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL … #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x) … #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x) … #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x) … /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ #define ANA_ACL_VCAP_S2_RLEG_STAT(r) … #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK … #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x) … #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x) … #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK … #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x) … #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x) … /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ #define ANA_ACL_VCAP_S2_FRAGMENT_CFG … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x) … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x) … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x) … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x) … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x) … #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x) … /* ANA_ACL:COMMON:OWN_UPSID */ #define ANA_ACL_OWN_UPSID(r) … #define ANA_ACL_OWN_UPSID_OWN_UPSID … #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x) … #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x) … /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) … #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA … #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL … #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x) … #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x) … /* ANA_ACL:CNT_A:CNT_A */ #define ANA_ACL_CNT_A(g) … /* ANA_ACL:CNT_B:CNT_B */ #define ANA_ACL_CNT_B(g) … /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ #define ANA_ACL_SEC_LOOKUP_STICKY(r) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x) … #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x) … /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ #define ANA_AC_POL_POL_UPD_INT_CFG … #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT … #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x) … #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x) … /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ #define ANA_AC_POL_BDLB_DLB_CTRL … #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS … #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT … #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA … #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA … #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x) … #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x) … /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ #define ANA_AC_POL_SLB_DLB_CTRL … #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS … #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT … #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA … #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA … #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x) … #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ #define ANA_AC_SDLB_XLB_START(g) … #define ANA_AC_SDLB_XLB_START_LBSET_START … #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x) … #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ #define ANA_AC_SDLB_PUP_INTERVAL(g) … #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL … #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x) … #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ #define ANA_AC_SDLB_PUP_CTRL(g) … #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT … #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x) … #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x) … #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA … #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x) … #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ #define ANA_AC_SDLB_LBGRP_MISC(g) … #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT … #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x) … #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) … #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS … #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x) … #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x) … /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x) … #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ #define ANA_AC_SDLB_PUP_TOKENS(g, r) … #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS … #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x) … #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:THRES */ #define ANA_AC_SDLB_THRES(g, r) … #define ANA_AC_SDLB_THRES_THRES … #define ANA_AC_SDLB_THRES_THRES_SET(x) … #define ANA_AC_SDLB_THRES_THRES_GET(x) … #define ANA_AC_SDLB_THRES_THRES_HYS … #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x) … #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ #define ANA_AC_SDLB_XLB_NEXT(g) … #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT … #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x) … #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x) … #define ANA_AC_SDLB_XLB_NEXT_LBGRP … #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x) … #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ #define ANA_AC_SDLB_INH_CTRL(g, r) … #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX … #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x) … #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x) … #define ANA_AC_SDLB_INH_CTRL_INH_MODE … #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x) … #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x) … #define ANA_AC_SDLB_INH_CTRL_INH_LB … #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x) … #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ #define ANA_AC_SDLB_INH_LBSET_ADDR(g) … #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR … #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x) … #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ #define ANA_AC_SDLB_DLB_MISC(g) … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x) … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x) … #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA … #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x) … #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x) … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x) … #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x) … /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ #define ANA_AC_SDLB_DLB_CFG(g) … #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA … #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x) … #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x) … #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL … #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x) … #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x) … #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS … #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x) … #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x) … #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS … #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x) … #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x) … #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL … #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x) … #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x) … #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL … #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x) … #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x) … #define ANA_AC_SDLB_DLB_CFG_DLB_MODE … #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x) … #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x) … #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK … #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x) … #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x) … /* ANA_CL:PORT:FILTER_CTRL */ #define ANA_CL_FILTER_CTRL(g) … #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS … #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x) … #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x) … #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS … #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x) … #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x) … #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA … #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x) … #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x) … /* ANA_CL:PORT:VLAN_FILTER_CTRL */ #define ANA_CL_VLAN_FILTER_CTRL(g, r) … #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA … #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS … #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x) … #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x) … /* ANA_CL:PORT:ETAG_FILTER_CTRL */ #define ANA_CL_ETAG_FILTER_CTRL(g) … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x) … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x) … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x) … #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x) … /* ANA_CL:PORT:VLAN_CTRL */ #define ANA_CL_VLAN_CTRL(g) … #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS … #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x) … #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA … #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x) … #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x) … #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL … #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x) … #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x) … #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA … #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x) … #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x) … #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT … #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x) … #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE … #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_PCP … #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_DEI … #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x) … #define ANA_CL_VLAN_CTRL_PORT_VID … #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x) … #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x) … /* ANA_CL:PORT:VLAN_CTRL_2 */ #define ANA_CL_VLAN_CTRL_2(g) … #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT … #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x) … #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x) … /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ #define ANA_CL_PCP_DEI_MAP_CFG(g, r) … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x) … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x) … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x) … #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x) … /* ANA_CL:PORT:QOS_CFG */ #define ANA_CL_QOS_CFG(g) … #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA … #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x) … #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x) … #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL … #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x) … #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x) … #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL … #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x) … #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x) … #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA … #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x) … #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x) … #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA … #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x) … #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x) … #define ANA_CL_QOS_CFG_KEEP_ENA … #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x) … #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x) … #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA … #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x) … #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x) … #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA … #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x) … #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x) … #define ANA_CL_QOS_CFG_DSCP_DP_ENA … #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x) … #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x) … #define ANA_CL_QOS_CFG_DSCP_QOS_ENA … #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x) … #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x) … #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL … #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x) … #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x) … #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL … #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x) … #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x) … /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ #define ANA_CL_CAPTURE_BPDU_CFG(g) … /* ANA_CL:PORT:ADV_CL_CFG_2 */ #define ANA_CL_ADV_CL_CFG_2(g, r) … #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA … #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x) … #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x) … #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA … #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x) … #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x) … /* ANA_CL:PORT:ADV_CL_CFG */ #define ANA_CL_ADV_CL_CFG(g, r) … #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL … #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x) … #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x) … #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA … #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x) … #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x) … /* ANA_CL:COMMON:OWN_UPSID */ #define ANA_CL_OWN_UPSID(r) … #define ANA_CL_OWN_UPSID_OWN_UPSID … #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x) … #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x) … /* ANA_CL:COMMON:DSCP_CFG */ #define ANA_CL_DSCP_CFG(r) … #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL … #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x) … #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x) … #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL … #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x) … #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x) … #define ANA_CL_DSCP_CFG_DSCP_DP_VAL … #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x) … #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x) … #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA … #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x) … #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x) … #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA … #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x) … #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x) … /* ANA_CL:COMMON:QOS_MAP_CFG */ #define ANA_CL_QOS_MAP_CFG(r) … #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL … #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x) … #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x) … /* ANA_L2:COMMON:FWD_CFG */ #define ANA_L2_FWD_CFG … #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL … #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x) … #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x) … #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA … #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x) … #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x) … #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA … #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x) … #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x) … #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA … #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x) … #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x) … #define ANA_L2_FWD_CFG_CPU_DMAC_QU … #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x) … #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x) … #define ANA_L2_FWD_CFG_LOOPBACK_ENA … #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x) … #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x) … #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA … #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x) … #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x) … #define ANA_L2_FWD_CFG_FILTER_MODE_SEL … #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x) … #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x) … #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA … #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x) … #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x) … #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA … #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x) … #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x) … #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA … #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x) … #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x) … #define ANA_L2_FWD_CFG_FWD_ENA … #define ANA_L2_FWD_CFG_FWD_ENA_SET(x) … #define ANA_L2_FWD_CFG_FWD_ENA_GET(x) … /* ANA_L2:COMMON:AUTO_LRN_CFG */ #define ANA_L2_AUTO_LRN_CFG … /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ #define ANA_L2_AUTO_LRN_CFG1 … /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ #define ANA_L2_AUTO_LRN_CFG2 … #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 … #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x) … #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x) … /* ANA_L2:COMMON:OWN_UPSID */ #define ANA_L2_OWN_UPSID(r) … #define ANA_L2_OWN_UPSID_OWN_UPSID … #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x) … #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x) … /* ANA_L2:ISDX:DLB_CFG */ #define ANA_L2_DLB_CFG(g) … #define ANA_L2_DLB_CFG_DLB_IDX … #define ANA_L2_DLB_CFG_DLB_IDX_SET(x) … #define ANA_L2_DLB_CFG_DLB_IDX_GET(x) … /* ANA_L2:ISDX:TSN_CFG */ #define ANA_L2_TSN_CFG(g) … #define ANA_L2_TSN_CFG_TSN_SFID … #define ANA_L2_TSN_CFG_TSN_SFID_SET(x) … #define ANA_L2_TSN_CFG_TSN_SFID_GET(x) … /* ANA_L3:COMMON:VLAN_CTRL */ #define ANA_L3_VLAN_CTRL … #define ANA_L3_VLAN_CTRL_VLAN_ENA … #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x) … #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x) … /* ANA_L3:VLAN:VLAN_CFG */ #define ANA_L3_VLAN_CFG(g) … #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR … #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_FID … #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA … #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA … #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS … #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS … #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA … #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA … #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x) … #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA … #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x) … #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x) … /* ANA_L3:VLAN:VLAN_MASK_CFG */ #define ANA_L3_VLAN_MASK_CFG(g) … /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ #define ANA_L3_VLAN_MASK_CFG1(g) … /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ #define ANA_L3_VLAN_MASK_CFG2(g) … #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 … #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x) … #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x) … /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ #define ASM_RX_IN_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ #define ASM_RX_SYMBOL_ERR_CNT(g) … /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ #define ASM_RX_PAUSE_CNT(g) … /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ #define ASM_RX_UNSUP_OPCODE_CNT(g) … /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ #define ASM_RX_OK_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ #define ASM_RX_BAD_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:RX_UC_CNT */ #define ASM_RX_UC_CNT(g) … /* ASM:DEV_STATISTICS:RX_MC_CNT */ #define ASM_RX_MC_CNT(g) … /* ASM:DEV_STATISTICS:RX_BC_CNT */ #define ASM_RX_BC_CNT(g) … /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ #define ASM_RX_CRC_ERR_CNT(g) … /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ #define ASM_RX_UNDERSIZE_CNT(g) … /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ #define ASM_RX_FRAGMENTS_CNT(g) … /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) … /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) … /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ #define ASM_RX_OVERSIZE_CNT(g) … /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ #define ASM_RX_JABBERS_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ #define ASM_RX_SIZE64_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ #define ASM_RX_SIZE65TO127_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ #define ASM_RX_SIZE128TO255_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ #define ASM_RX_SIZE256TO511_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ #define ASM_RX_SIZE512TO1023_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ #define ASM_RX_SIZE1024TO1518_CNT(g) … /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ #define ASM_RX_SIZE1519TOMAX_CNT(g) … /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ #define ASM_RX_IPG_SHRINK_CNT(g) … /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ #define ASM_TX_OUT_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ #define ASM_TX_PAUSE_CNT(g) … /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ #define ASM_TX_OK_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:TX_UC_CNT */ #define ASM_TX_UC_CNT(g) … /* ASM:DEV_STATISTICS:TX_MC_CNT */ #define ASM_TX_MC_CNT(g) … /* ASM:DEV_STATISTICS:TX_BC_CNT */ #define ASM_TX_BC_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ #define ASM_TX_SIZE64_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ #define ASM_TX_SIZE65TO127_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ #define ASM_TX_SIZE128TO255_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ #define ASM_TX_SIZE256TO511_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ #define ASM_TX_SIZE512TO1023_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ #define ASM_TX_SIZE1024TO1518_CNT(g) … /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ #define ASM_TX_SIZE1519TOMAX_CNT(g) … /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ #define ASM_RX_ALIGNMENT_LOST_CNT(g) … /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ #define ASM_RX_TAGGED_FRMS_CNT(g) … /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ #define ASM_RX_UNTAGGED_FRMS_CNT(g) … /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ #define ASM_TX_TAGGED_FRMS_CNT(g) … /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ #define ASM_TX_UNTAGGED_FRMS_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ #define ASM_PMAC_RX_PAUSE_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ #define ASM_PMAC_RX_OK_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ #define ASM_PMAC_RX_BAD_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ #define ASM_PMAC_RX_UC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ #define ASM_PMAC_RX_MC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ #define ASM_PMAC_RX_BC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ #define ASM_PMAC_RX_CRC_ERR_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ #define ASM_PMAC_RX_UNDERSIZE_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ #define ASM_PMAC_RX_FRAGMENTS_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ #define ASM_PMAC_RX_OVERSIZE_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ #define ASM_PMAC_RX_JABBERS_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ #define ASM_PMAC_RX_SIZE64_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ #define ASM_PMAC_RX_SIZE65TO127_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ #define ASM_PMAC_RX_SIZE128TO255_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ #define ASM_PMAC_RX_SIZE256TO511_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ #define ASM_PMAC_TX_PAUSE_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ #define ASM_PMAC_TX_OK_BYTES_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ #define ASM_PMAC_TX_UC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ #define ASM_PMAC_TX_MC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ #define ASM_PMAC_TX_BC_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ #define ASM_PMAC_TX_SIZE64_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ #define ASM_PMAC_TX_SIZE65TO127_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ #define ASM_PMAC_TX_SIZE128TO255_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ #define ASM_PMAC_TX_SIZE256TO511_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) … /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) … /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) … /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ #define ASM_MM_RX_SMD_ERR_CNT(g) … /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) … /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ #define ASM_MM_RX_MERGE_FRAG_CNT(g) … /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ #define ASM_MM_TX_PFRAGMENT_CNT(g) … /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ #define ASM_TX_MULTI_COLL_CNT(g) … /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ #define ASM_TX_LATE_COLL_CNT(g) … /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ #define ASM_TX_XCOLL_CNT(g) … /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ #define ASM_TX_DEFER_CNT(g) … /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ #define ASM_TX_XDEFER_CNT(g) … /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ #define ASM_TX_BACKOFF1_CNT(g) … /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ #define ASM_TX_CSENSE_CNT(g) … /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ #define ASM_RX_IN_BYTES_MSB_CNT(g) … #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT … #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x) … #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ #define ASM_RX_OK_BYTES_MSB_CNT(g) … #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT … #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x) … #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) … #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT … #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x) … #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ #define ASM_RX_BAD_BYTES_MSB_CNT(g) … #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT … #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x) … #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) … #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT … #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x) … #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ #define ASM_TX_OUT_BYTES_MSB_CNT(g) … #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT … #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x) … #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ #define ASM_TX_OK_BYTES_MSB_CNT(g) … #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT … #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x) … #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) … #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT … #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x) … #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x) … /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ #define ASM_RX_SYNC_LOST_ERR_CNT(g) … /* ASM:CFG:STAT_CFG */ #define ASM_STAT_CFG … #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT … #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x) … #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x) … /* ASM:CFG:PORT_CFG */ #define ASM_PORT_CFG(r) … #define ASM_PORT_CFG_CSC_STAT_DIS … #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x) … #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x) … #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA … #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x) … #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x) … #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA … #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x) … #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x) … #define ASM_PORT_CFG_NO_PREAMBLE_ENA … #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x) … #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x) … #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA … #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x) … #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x) … #define ASM_PORT_CFG_FRM_AGING_DIS … #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x) … #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x) … #define ASM_PORT_CFG_PAD_ENA … #define ASM_PORT_CFG_PAD_ENA_SET(x) … #define ASM_PORT_CFG_PAD_ENA_GET(x) … #define ASM_PORT_CFG_INJ_DISCARD_CFG … #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x) … #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x) … #define ASM_PORT_CFG_INJ_FORMAT_CFG … #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x) … #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x) … #define ASM_PORT_CFG_VSTAX2_AWR_ENA … #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x) … #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x) … #define ASM_PORT_CFG_PFRM_FLUSH … #define ASM_PORT_CFG_PFRM_FLUSH_SET(x) … #define ASM_PORT_CFG_PFRM_FLUSH_GET(x) … /* ASM:RAM_CTRL:RAM_INIT */ #define ASM_RAM_INIT … #define ASM_RAM_INIT_RAM_INIT … #define ASM_RAM_INIT_RAM_INIT_SET(x) … #define ASM_RAM_INIT_RAM_INIT_GET(x) … #define ASM_RAM_INIT_RAM_CFG_HOOK … #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ #define CLKGEN_LCPLL1_CORE_CLK_CFG … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x) … #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x) … /* CPU:CPU_REGS:PROC_CTRL */ #define CPU_PROC_CTRL … #define CPU_PROC_CTRL_AARCH64_MODE_ENA … #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x) … #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x) … #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS … #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x) … #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x) … #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS … #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x) … #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x) … #define CPU_PROC_CTRL_BE_EXCEP_MODE … #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x) … #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x) … #define CPU_PROC_CTRL_VINITHI … #define CPU_PROC_CTRL_VINITHI_SET(x) … #define CPU_PROC_CTRL_VINITHI_GET(x) … #define CPU_PROC_CTRL_CFGTE … #define CPU_PROC_CTRL_CFGTE_SET(x) … #define CPU_PROC_CTRL_CFGTE_GET(x) … #define CPU_PROC_CTRL_CP15S_DISABLE … #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x) … #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x) … #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE … #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x) … #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x) … #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA … #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x) … #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x) … #define CPU_PROC_CTRL_ACP_AWCACHE … #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x) … #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x) … #define CPU_PROC_CTRL_ACP_ARCACHE … #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x) … #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x) … #define CPU_PROC_CTRL_L2_FLUSH_REQ … #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x) … #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x) … #define CPU_PROC_CTRL_ACP_DISABLE … #define CPU_PROC_CTRL_ACP_DISABLE_SET(x) … #define CPU_PROC_CTRL_ACP_DISABLE_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV10G_MAC_ENA_CFG(t) … #define DEV10G_MAC_ENA_CFG_RX_ENA … #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x) … #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x) … #define DEV10G_MAC_ENA_CFG_TX_ENA … #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x) … #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ #define DEV10G_MAC_MAXLEN_CFG(t) … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x) … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x) … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x) … #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ #define DEV10G_MAC_NUM_TAGS_CFG(t) … #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS … #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x) … #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ #define DEV10G_MAC_TAGS_CFG(t, r) … #define DEV10G_MAC_TAGS_CFG_TAG_ID … #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x) … #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x) … #define DEV10G_MAC_TAGS_CFG_TAG_ENA … #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x) … #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ #define DEV10G_MAC_ADV_CHK_CFG(t) … #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA … #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA … #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA … #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS … #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA … #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA … #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x) … #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA … #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x) … #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ #define DEV10G_MAC_TX_MONITOR_STICKY(t) … #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY … #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY … #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY … #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY … #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY … #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x) … #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x) … /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ #define DEV10G_DEV_RST_CTRL(t) … #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA … #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x) … #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x) … #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS … #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x) … #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x) … #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS … #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x) … #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x) … #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL … #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x) … #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x) … #define DEV10G_DEV_RST_CTRL_SPEED_SEL … #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x) … #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x) … #define DEV10G_DEV_RST_CTRL_PCS_TX_RST … #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x) … #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x) … #define DEV10G_DEV_RST_CTRL_PCS_RX_RST … #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x) … #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x) … #define DEV10G_DEV_RST_CTRL_MAC_TX_RST … #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x) … #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x) … #define DEV10G_DEV_RST_CTRL_MAC_RX_RST … #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x) … #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x) … /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ #define DEV10G_PCS25G_CFG(t) … #define DEV10G_PCS25G_CFG_PCS25G_ENA … #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x) … #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV25G_MAC_ENA_CFG(t) … #define DEV25G_MAC_ENA_CFG_RX_ENA … #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x) … #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x) … #define DEV25G_MAC_ENA_CFG_TX_ENA … #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x) … #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ #define DEV25G_MAC_MAXLEN_CFG(t) … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x) … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x) … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x) … #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ #define DEV25G_MAC_ADV_CHK_CFG(t) … #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA … #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA … #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA … #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS … #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA … #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA … #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x) … #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA … #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x) … #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x) … /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ #define DEV25G_DEV_RST_CTRL(t) … #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA … #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x) … #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x) … #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS … #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x) … #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x) … #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS … #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x) … #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x) … #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL … #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x) … #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x) … #define DEV25G_DEV_RST_CTRL_SPEED_SEL … #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x) … #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x) … #define DEV25G_DEV_RST_CTRL_PCS_TX_RST … #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x) … #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x) … #define DEV25G_DEV_RST_CTRL_PCS_RX_RST … #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x) … #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x) … #define DEV25G_DEV_RST_CTRL_MAC_TX_RST … #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x) … #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x) … #define DEV25G_DEV_RST_CTRL_MAC_RX_RST … #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x) … #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x) … /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ #define DEV25G_PCS25G_CFG(t) … #define DEV25G_PCS25G_CFG_PCS25G_ENA … #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x) … #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x) … /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ #define DEV25G_PCS25G_SD_CFG(t) … #define DEV25G_PCS25G_SD_CFG_SD_SEL … #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x) … #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x) … #define DEV25G_PCS25G_SD_CFG_SD_POL … #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x) … #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x) … #define DEV25G_PCS25G_SD_CFG_SD_ENA … #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x) … #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x) … /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ #define DEV2G5_DEV_RST_CTRL(t) … #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS … #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x) … #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x) … #define DEV2G5_DEV_RST_CTRL_SPEED_SEL … #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x) … #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x) … #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST … #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x) … #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST … #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x) … #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST … #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x) … #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST … #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x) … #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST … #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x) … #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST … #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x) … #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV2G5_MAC_ENA_CFG(t) … #define DEV2G5_MAC_ENA_CFG_RX_ENA … #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x) … #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x) … #define DEV2G5_MAC_ENA_CFG_TX_ENA … #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x) … #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ #define DEV2G5_MAC_MODE_CFG(t) … #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA … #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x) … #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x) … #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA … #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x) … #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x) … #define DEV2G5_MAC_MODE_CFG_FDX_ENA … #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x) … #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ #define DEV2G5_MAC_MAXLEN_CFG(t) … #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN … #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x) … #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ #define DEV2G5_MAC_TAGS_CFG(t) … #define DEV2G5_MAC_TAGS_CFG_TAG_ID … #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x) … #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x) … #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA … #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x) … #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x) … #define DEV2G5_MAC_TAGS_CFG_PB_ENA … #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x) … #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x) … #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA … #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x) … #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ #define DEV2G5_MAC_TAGS_CFG2(t) … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x) … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x) … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x) … #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ #define DEV2G5_MAC_ADV_CHK_CFG(t) … #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA … #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x) … #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ #define DEV2G5_MAC_IFG_CFG(t) … #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK … #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x) … #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x) … #define DEV2G5_MAC_IFG_CFG_TX_IFG … #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x) … #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x) … #define DEV2G5_MAC_IFG_CFG_RX_IFG2 … #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x) … #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x) … #define DEV2G5_MAC_IFG_CFG_RX_IFG1 … #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x) … #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x) … /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ #define DEV2G5_MAC_HDX_CFG(t) … #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC … #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x) … #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x) … #define DEV2G5_MAC_HDX_CFG_SEED … #define DEV2G5_MAC_HDX_CFG_SEED_SET(x) … #define DEV2G5_MAC_HDX_CFG_SEED_GET(x) … #define DEV2G5_MAC_HDX_CFG_SEED_LOAD … #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x) … #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x) … #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA … #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x) … #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x) … #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS … #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x) … #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ #define DEV2G5_PCS1G_CFG(t) … #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE … #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x) … #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x) … #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA … #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x) … #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x) … #define DEV2G5_PCS1G_CFG_PCS_ENA … #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x) … #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ #define DEV2G5_PCS1G_MODE_CFG(t) … #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA … #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x) … #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x) … #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA … #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x) … #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x) … #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA … #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x) … #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ #define DEV2G5_PCS1G_SD_CFG(t) … #define DEV2G5_PCS1G_SD_CFG_SD_SEL … #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x) … #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x) … #define DEV2G5_PCS1G_SD_CFG_SD_POL … #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x) … #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x) … #define DEV2G5_PCS1G_SD_CFG_SD_ENA … #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x) … #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ #define DEV2G5_PCS1G_ANEG_CFG(t) … #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY … #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x) … #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x) … #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA … #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x) … #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x) … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x) … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x) … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x) … #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ #define DEV2G5_PCS1G_LB_CFG(t) … #define DEV2G5_PCS1G_LB_CFG_RA_ENA … #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x) … #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x) … #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA … #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x) … #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x) … #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA … #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x) … #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ #define DEV2G5_PCS1G_ANEG_STATUS(t) … #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY … #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_PR … #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY … #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE … #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x) … #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ #define DEV2G5_PCS1G_LINK_STATUS(t) … #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR … #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x) … #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x) … #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT … #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x) … #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x) … #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS … #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x) … #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x) … #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS … #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x) … #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x) … /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ #define DEV2G5_PCS1G_STICKY(t) … #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY … #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x) … #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x) … #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY … #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x) … #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x) … /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ #define DEV2G5_PCS_FX100_CFG(t) … #define DEV2G5_PCS_FX100_CFG_SD_SEL … #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x) … #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x) … #define DEV2G5_PCS_FX100_CFG_SD_POL … #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x) … #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x) … #define DEV2G5_PCS_FX100_CFG_SD_ENA … #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA … #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA … #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_RXBITSEL … #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x) … #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x) … #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG … #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x) … #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x) … #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA … #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER … #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x) … #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x) … #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA … #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA … #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA … #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x) … #define DEV2G5_PCS_FX100_CFG_PCS_ENA … #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x) … #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x) … /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ #define DEV2G5_PCS_FX100_STATUS(t) … #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP … #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x) … #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x) … #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY … #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x) … #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x) … #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY … #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x) … #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x) … #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY … #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x) … #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x) … #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY … #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x) … #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x) … #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS … #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x) … #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x) … #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT … #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x) … #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x) … #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS … #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x) … #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ #define DEV5G_MAC_ENA_CFG(t) … #define DEV5G_MAC_ENA_CFG_RX_ENA … #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x) … #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x) … #define DEV5G_MAC_ENA_CFG_TX_ENA … #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x) … #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ #define DEV5G_MAC_MAXLEN_CFG(t) … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x) … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x) … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x) … #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x) … /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ #define DEV5G_MAC_ADV_CHK_CFG(t) … #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA … #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA … #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA … #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS … #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA … #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA … #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x) … #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA … #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x) … #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ #define DEV5G_RX_SYMBOL_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ #define DEV5G_RX_PAUSE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ #define DEV5G_RX_UNSUP_OPCODE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ #define DEV5G_RX_UC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ #define DEV5G_RX_MC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ #define DEV5G_RX_BC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ #define DEV5G_RX_CRC_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ #define DEV5G_RX_UNDERSIZE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ #define DEV5G_RX_FRAGMENTS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ #define DEV5G_RX_OVERSIZE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ #define DEV5G_RX_JABBERS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ #define DEV5G_RX_SIZE64_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ #define DEV5G_RX_SIZE65TO127_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ #define DEV5G_RX_SIZE128TO255_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ #define DEV5G_RX_SIZE256TO511_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ #define DEV5G_RX_SIZE512TO1023_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ #define DEV5G_RX_SIZE1024TO1518_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ #define DEV5G_RX_SIZE1519TOMAX_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ #define DEV5G_RX_IPG_SHRINK_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ #define DEV5G_TX_PAUSE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ #define DEV5G_TX_UC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ #define DEV5G_TX_MC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ #define DEV5G_TX_BC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ #define DEV5G_TX_SIZE64_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ #define DEV5G_TX_SIZE65TO127_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ #define DEV5G_TX_SIZE128TO255_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ #define DEV5G_TX_SIZE256TO511_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ #define DEV5G_TX_SIZE512TO1023_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ #define DEV5G_TX_SIZE1024TO1518_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ #define DEV5G_TX_SIZE1519TOMAX_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ #define DEV5G_RX_TAGGED_FRMS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ #define DEV5G_TX_TAGGED_FRMS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ #define DEV5G_PMAC_RX_PAUSE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ #define DEV5G_PMAC_RX_UC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ #define DEV5G_PMAC_RX_MC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ #define DEV5G_PMAC_RX_BC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ #define DEV5G_PMAC_RX_JABBERS_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ #define DEV5G_PMAC_RX_SIZE64_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ #define DEV5G_PMAC_TX_PAUSE_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ #define DEV5G_PMAC_TX_UC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ #define DEV5G_PMAC_TX_MC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ #define DEV5G_PMAC_TX_BC_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ #define DEV5G_PMAC_TX_SIZE64_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ #define DEV5G_MM_RX_SMD_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ #define DEV5G_MM_TX_PFRAGMENT_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ #define DEV5G_RX_IN_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ #define DEV5G_RX_IN_BYTES_MSB_CNT(t) … #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT … #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x) … #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ #define DEV5G_RX_OK_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ #define DEV5G_RX_OK_BYTES_MSB_CNT(t) … #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT … #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x) … #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ #define DEV5G_RX_BAD_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) … #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT … #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x) … #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ #define DEV5G_TX_OUT_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) … #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT … #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x) … #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ #define DEV5G_TX_OK_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ #define DEV5G_TX_OK_BYTES_MSB_CNT(t) … #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT … #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x) … #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) … #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT … #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x) … #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) … #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT … #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x) … #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) … /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) … #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT … #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x) … #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x) … /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ #define DEV5G_DEV_RST_CTRL(t) … #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA … #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x) … #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x) … #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS … #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x) … #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x) … #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS … #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x) … #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x) … #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL … #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x) … #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x) … #define DEV5G_DEV_RST_CTRL_SPEED_SEL … #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x) … #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x) … #define DEV5G_DEV_RST_CTRL_PCS_TX_RST … #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x) … #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x) … #define DEV5G_DEV_RST_CTRL_PCS_RX_RST … #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x) … #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x) … #define DEV5G_DEV_RST_CTRL_MAC_TX_RST … #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x) … #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x) … #define DEV5G_DEV_RST_CTRL_MAC_RX_RST … #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x) … #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x) … /* DSM:RAM_CTRL:RAM_INIT */ #define DSM_RAM_INIT … #define DSM_RAM_INIT_RAM_INIT … #define DSM_RAM_INIT_RAM_INIT_SET(x) … #define DSM_RAM_INIT_RAM_INIT_GET(x) … #define DSM_RAM_INIT_RAM_CFG_HOOK … #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* DSM:CFG:BUF_CFG */ #define DSM_BUF_CFG(r) … #define DSM_BUF_CFG_CSC_STAT_DIS … #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x) … #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x) … #define DSM_BUF_CFG_AGING_ENA … #define DSM_BUF_CFG_AGING_ENA_SET(x) … #define DSM_BUF_CFG_AGING_ENA_GET(x) … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x) … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x) … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x) … #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x) … /* DSM:CFG:DEV_TX_STOP_WM_CFG */ #define DSM_DEV_TX_STOP_WM_CFG(r) … #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA … #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x) … #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA … #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x) … #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x) … /* DSM:CFG:RX_PAUSE_CFG */ #define DSM_RX_PAUSE_CFG(r) … #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN … #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x) … #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x) … #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL … #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x) … #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x) … /* DSM:CFG:MAC_CFG */ #define DSM_MAC_CFG(r) … #define DSM_MAC_CFG_TX_PAUSE_VAL … #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x) … #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x) … #define DSM_MAC_CFG_HDX_BACKPREASSURE … #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x) … #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x) … #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE … #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x) … #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x) … #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF … #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x) … #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x) … /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) … #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH … #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x) … #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x) … /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ #define DSM_MAC_ADDR_BASE_LOW_CFG(r) … #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW … #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x) … #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x) … /* DSM:CFG:TAXI_CAL_CFG */ #define DSM_TAXI_CAL_CFG(r) … #define DSM_TAXI_CAL_CFG_CAL_IDX … #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x) … #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x) … #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN … #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x) … #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x) … #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL … #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x) … #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x) … #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL … #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x) … #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x) … #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA … #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x) … #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x) … /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ #define EACL_VCAP_ES2_KEY_SEL(g, r) … #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL … #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x) … #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x) … #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL … #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x) … #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x) … #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL … #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x) … #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x) … #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA … #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x) … #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x) … /* EACL:CNT_TBL:ES2_CNT */ #define EACL_ES2_CNT(g) … /* EACL:POL_CFG:POL_EACL_CFG */ #define EACL_POL_EACL_CFG … #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED … #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x) … #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x) … #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY … #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x) … #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x) … #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY … #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x) … #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE … #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN … #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_INIT … #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x) … #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x) … /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ #define EACL_SEC_LOOKUP_STICKY(r) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x) … #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x) … /* EACL:RAM_CTRL:RAM_INIT */ #define EACL_RAM_INIT … #define EACL_RAM_INIT_RAM_INIT … #define EACL_RAM_INIT_RAM_INIT_SET(x) … #define EACL_RAM_INIT_RAM_INIT_GET(x) … #define EACL_RAM_INIT_RAM_CFG_HOOK … #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* FDMA:FDMA:FDMA_CH_ACTIVATE */ #define FDMA_CH_ACTIVATE … #define FDMA_CH_ACTIVATE_CH_ACTIVATE … #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x) … #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x) … /* FDMA:FDMA:FDMA_CH_RELOAD */ #define FDMA_CH_RELOAD … #define FDMA_CH_RELOAD_CH_RELOAD … #define FDMA_CH_RELOAD_CH_RELOAD_SET(x) … #define FDMA_CH_RELOAD_CH_RELOAD_GET(x) … /* FDMA:FDMA:FDMA_CH_DISABLE */ #define FDMA_CH_DISABLE … #define FDMA_CH_DISABLE_CH_DISABLE … #define FDMA_CH_DISABLE_CH_DISABLE_SET(x) … #define FDMA_CH_DISABLE_CH_DISABLE_GET(x) … /* FDMA:FDMA:FDMA_DCB_LLP */ #define FDMA_DCB_LLP(r) … /* FDMA:FDMA:FDMA_DCB_LLP1 */ #define FDMA_DCB_LLP1(r) … /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ #define FDMA_DCB_LLP_PREV(r) … /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ #define FDMA_DCB_LLP_PREV1(r) … /* FDMA:FDMA:FDMA_CH_CFG */ #define FDMA_CH_CFG(r) … #define FDMA_CH_CFG_CH_XTR_STATUS_MODE … #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x) … #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x) … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x) … #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x) … #define FDMA_CH_CFG_CH_INJ_PORT … #define FDMA_CH_CFG_CH_INJ_PORT_SET(x) … #define FDMA_CH_CFG_CH_INJ_PORT_GET(x) … #define FDMA_CH_CFG_CH_DCB_DB_CNT … #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x) … #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x) … #define FDMA_CH_CFG_CH_MEM … #define FDMA_CH_CFG_CH_MEM_SET(x) … #define FDMA_CH_CFG_CH_MEM_GET(x) … /* FDMA:FDMA:FDMA_CH_TRANSLATE */ #define FDMA_CH_TRANSLATE(r) … #define FDMA_CH_TRANSLATE_OFFSET … #define FDMA_CH_TRANSLATE_OFFSET_SET(x) … #define FDMA_CH_TRANSLATE_OFFSET_GET(x) … /* FDMA:FDMA:FDMA_XTR_CFG */ #define FDMA_XTR_CFG … #define FDMA_XTR_CFG_XTR_FIFO_WM … #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x) … #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x) … #define FDMA_XTR_CFG_XTR_ARB_SAT … #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x) … #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x) … /* FDMA:FDMA:FDMA_PORT_CTRL */ #define FDMA_PORT_CTRL(r) … #define FDMA_PORT_CTRL_INJ_STOP … #define FDMA_PORT_CTRL_INJ_STOP_SET(x) … #define FDMA_PORT_CTRL_INJ_STOP_GET(x) … #define FDMA_PORT_CTRL_INJ_STOP_FORCE … #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x) … #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x) … #define FDMA_PORT_CTRL_XTR_STOP … #define FDMA_PORT_CTRL_XTR_STOP_SET(x) … #define FDMA_PORT_CTRL_XTR_STOP_GET(x) … #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY … #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x) … #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x) … #define FDMA_PORT_CTRL_XTR_BUF_RST … #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x) … #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x) … /* FDMA:FDMA:FDMA_INTR_DCB */ #define FDMA_INTR_DCB … #define FDMA_INTR_DCB_INTR_DCB … #define FDMA_INTR_DCB_INTR_DCB_SET(x) … #define FDMA_INTR_DCB_INTR_DCB_GET(x) … /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ #define FDMA_INTR_DCB_ENA … #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA … #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x) … #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x) … /* FDMA:FDMA:FDMA_INTR_DB */ #define FDMA_INTR_DB … #define FDMA_INTR_DB_INTR_DB … #define FDMA_INTR_DB_INTR_DB_SET(x) … #define FDMA_INTR_DB_INTR_DB_GET(x) … /* FDMA:FDMA:FDMA_INTR_DB_ENA */ #define FDMA_INTR_DB_ENA … #define FDMA_INTR_DB_ENA_INTR_DB_ENA … #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x) … #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x) … /* FDMA:FDMA:FDMA_INTR_ERR */ #define FDMA_INTR_ERR … #define FDMA_INTR_ERR_INTR_PORT_ERR … #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x) … #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x) … #define FDMA_INTR_ERR_INTR_CH_ERR … #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x) … #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x) … /* FDMA:FDMA:FDMA_ERRORS */ #define FDMA_ERRORS … #define FDMA_ERRORS_ERR_XTR_WR … #define FDMA_ERRORS_ERR_XTR_WR_SET(x) … #define FDMA_ERRORS_ERR_XTR_WR_GET(x) … #define FDMA_ERRORS_ERR_XTR_OVF … #define FDMA_ERRORS_ERR_XTR_OVF_SET(x) … #define FDMA_ERRORS_ERR_XTR_OVF_GET(x) … #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF … #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x) … #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x) … #define FDMA_ERRORS_ERR_DCB_XTR_DATAL … #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x) … #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x) … #define FDMA_ERRORS_ERR_DCB_RD … #define FDMA_ERRORS_ERR_DCB_RD_SET(x) … #define FDMA_ERRORS_ERR_DCB_RD_GET(x) … #define FDMA_ERRORS_ERR_INJ_RD … #define FDMA_ERRORS_ERR_INJ_RD_SET(x) … #define FDMA_ERRORS_ERR_INJ_RD_GET(x) … #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC … #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x) … #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x) … #define FDMA_ERRORS_ERR_CH_WR … #define FDMA_ERRORS_ERR_CH_WR_SET(x) … #define FDMA_ERRORS_ERR_CH_WR_GET(x) … /* FDMA:FDMA:FDMA_ERRORS_2 */ #define FDMA_ERRORS_2 … #define FDMA_ERRORS_2_ERR_XTR_FRAG … #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x) … #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x) … /* FDMA:FDMA:FDMA_CTRL */ #define FDMA_CTRL … #define FDMA_CTRL_NRESET … #define FDMA_CTRL_NRESET_SET(x) … #define FDMA_CTRL_NRESET_GET(x) … /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ #define GCB_CHIP_ID … #define GCB_CHIP_ID_REV_ID … #define GCB_CHIP_ID_REV_ID_SET(x) … #define GCB_CHIP_ID_REV_ID_GET(x) … #define GCB_CHIP_ID_PART_ID … #define GCB_CHIP_ID_PART_ID_SET(x) … #define GCB_CHIP_ID_PART_ID_GET(x) … #define GCB_CHIP_ID_MFG_ID … #define GCB_CHIP_ID_MFG_ID_SET(x) … #define GCB_CHIP_ID_MFG_ID_GET(x) … #define GCB_CHIP_ID_ONE … #define GCB_CHIP_ID_ONE_SET(x) … #define GCB_CHIP_ID_ONE_GET(x) … /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ #define GCB_SOFT_RST … #define GCB_SOFT_RST_SOFT_NON_CFG_RST … #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x) … #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x) … #define GCB_SOFT_RST_SOFT_SWC_RST … #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x) … #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x) … #define GCB_SOFT_RST_SOFT_CHIP_RST … #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x) … #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x) … /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ #define GCB_HW_SGPIO_SD_CFG … #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA … #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x) … #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x) … #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL … #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x) … #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x) … /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) … #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL … #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x) … #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x) … /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ #define GCB_SIO_CLOCK(g) … #define GCB_SIO_CLOCK_SIO_CLK_FREQ … #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x) … #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x) … #define GCB_SIO_CLOCK_SYS_CLK_PERIOD … #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x) … #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x) … /* HSCH:HSCH_CFG:CIR_CFG */ #define HSCH_CIR_CFG(g) … #define HSCH_CIR_CFG_CIR_RATE … #define HSCH_CIR_CFG_CIR_RATE_SET(x) … #define HSCH_CIR_CFG_CIR_RATE_GET(x) … #define HSCH_CIR_CFG_CIR_BURST … #define HSCH_CIR_CFG_CIR_BURST_SET(x) … #define HSCH_CIR_CFG_CIR_BURST_GET(x) … /* HSCH:HSCH_CFG:EIR_CFG */ #define HSCH_EIR_CFG(g) … #define HSCH_EIR_CFG_EIR_RATE … #define HSCH_EIR_CFG_EIR_RATE_SET(x) … #define HSCH_EIR_CFG_EIR_RATE_GET(x) … #define HSCH_EIR_CFG_EIR_BURST … #define HSCH_EIR_CFG_EIR_BURST_SET(x) … #define HSCH_EIR_CFG_EIR_BURST_GET(x) … /* HSCH:HSCH_CFG:SE_CFG */ #define HSCH_SE_CFG(g) … #define HSCH_SE_CFG_SE_DWRR_CNT … #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x) … #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x) … #define HSCH_SE_CFG_SE_AVB_ENA … #define HSCH_SE_CFG_SE_AVB_ENA_SET(x) … #define HSCH_SE_CFG_SE_AVB_ENA_GET(x) … #define HSCH_SE_CFG_SE_FRM_MODE … #define HSCH_SE_CFG_SE_FRM_MODE_SET(x) … #define HSCH_SE_CFG_SE_FRM_MODE_GET(x) … #define HSCH_SE_CFG_SE_DWRR_FRM_MODE … #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x) … #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x) … #define HSCH_SE_CFG_SE_STOP … #define HSCH_SE_CFG_SE_STOP_SET(x) … #define HSCH_SE_CFG_SE_STOP_GET(x) … /* HSCH:HSCH_CFG:SE_CONNECT */ #define HSCH_SE_CONNECT(g) … #define HSCH_SE_CONNECT_SE_LEAK_LINK … #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x) … #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x) … /* HSCH:HSCH_CFG:SE_DLB_SENSE */ #define HSCH_SE_DLB_SENSE(g) … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA … #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x) … #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x) … /* HSCH:HSCH_DWRR:DWRR_ENTRY */ #define HSCH_DWRR_ENTRY(g) … #define HSCH_DWRR_ENTRY_DWRR_COST … #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x) … #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x) … #define HSCH_DWRR_ENTRY_DWRR_BALANCE … #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x) … #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x) … /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ #define HSCH_HSCH_CFG_CFG … #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX … #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x) … #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x) … #define HSCH_HSCH_CFG_CFG_HSCH_LAYER … #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x) … #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x) … #define HSCH_HSCH_CFG_CFG_CSR_GRANT … #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x) … #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x) … /* HSCH:HSCH_MISC:SYS_CLK_PER */ #define HSCH_SYS_CLK_PER … #define HSCH_SYS_CLK_PER_100PS … #define HSCH_SYS_CLK_PER_100PS_SET(x) … #define HSCH_SYS_CLK_PER_100PS_GET(x) … /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ #define HSCH_HSCH_TIMER_CFG(g, r) … #define HSCH_HSCH_TIMER_CFG_LEAK_TIME … #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x) … #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x) … /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ #define HSCH_HSCH_LEAK_CFG(g, r) … #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST … #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x) … #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x) … #define HSCH_HSCH_LEAK_CFG_LEAK_ERR … #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x) … #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x) … /* HSCH:SYSTEM:FLUSH_CTRL */ #define HSCH_FLUSH_CTRL … #define HSCH_FLUSH_CTRL_FLUSH_ENA … #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_SRC … #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_DST … #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_PORT … #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_QUEUE … #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_SE … #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x) … #define HSCH_FLUSH_CTRL_FLUSH_HIER … #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x) … #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x) … /* HSCH:SYSTEM:PORT_MODE */ #define HSCH_PORT_MODE(r) … #define HSCH_PORT_MODE_DEQUEUE_DIS … #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x) … #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x) … #define HSCH_PORT_MODE_AGE_DIS … #define HSCH_PORT_MODE_AGE_DIS_SET(x) … #define HSCH_PORT_MODE_AGE_DIS_GET(x) … #define HSCH_PORT_MODE_TRUNC_ENA … #define HSCH_PORT_MODE_TRUNC_ENA_SET(x) … #define HSCH_PORT_MODE_TRUNC_ENA_GET(x) … #define HSCH_PORT_MODE_EIR_REMARK_ENA … #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x) … #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x) … #define HSCH_PORT_MODE_CPU_PRIO_MODE … #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x) … #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x) … /* HSCH:SYSTEM:OUTB_SHARE_ENA */ #define HSCH_OUTB_SHARE_ENA(r) … #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA … #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x) … #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x) … /* HSCH:MMGT:RESET_CFG */ #define HSCH_RESET_CFG … #define HSCH_RESET_CFG_CORE_ENA … #define HSCH_RESET_CFG_CORE_ENA_SET(x) … #define HSCH_RESET_CFG_CORE_ENA_GET(x) … /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ #define HSCH_TAS_STATEMACHINE_CFG … #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY … #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x) … #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x) … /* LRN:COMMON:COMMON_ACCESS_CTRL */ #define LRN_COMMON_ACCESS_CTRL … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x) … #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x) … #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT … #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x) … #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x) … /* LRN:COMMON:MAC_ACCESS_CFG_0 */ #define LRN_MAC_ACCESS_CFG_0 … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x) … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x) … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x) … #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x) … /* LRN:COMMON:MAC_ACCESS_CFG_1 */ #define LRN_MAC_ACCESS_CFG_1 … /* LRN:COMMON:MAC_ACCESS_CFG_2 */ #define LRN_MAC_ACCESS_CFG_2 … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x) … #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x) … /* LRN:COMMON:MAC_ACCESS_CFG_3 */ #define LRN_MAC_ACCESS_CFG_3 … #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX … #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x) … #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x) … /* LRN:COMMON:SCAN_NEXT_CFG */ #define LRN_SCAN_NEXT_CFG … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL … #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA … #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x) … #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x) … #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA … #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA … #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x) … #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA … #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x) … #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x) … /* LRN:COMMON:SCAN_NEXT_CFG_1 */ #define LRN_SCAN_NEXT_CFG_1 … #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR … #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x) … #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x) … #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK … #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x) … #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x) … /* LRN:COMMON:AUTOAGE_CFG */ #define LRN_AUTOAGE_CFG(r) … #define LRN_AUTOAGE_CFG_UNIT_SIZE … #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x) … #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x) … #define LRN_AUTOAGE_CFG_PERIOD_VAL … #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x) … #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x) … /* LRN:COMMON:AUTOAGE_CFG_1 */ #define LRN_AUTOAGE_CFG_1 … #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA … #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x) … #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x) … #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN … #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x) … #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x) … #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS … #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x) … #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x) … #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA … #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x) … #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA … #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x) … #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x) … /* LRN:COMMON:AUTOAGE_CFG_2 */ #define LRN_AUTOAGE_CFG_2 … #define LRN_AUTOAGE_CFG_2_NEXT_ROW … #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x) … #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x) … #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS … #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x) … #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x) … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ #define PCEP_RCTRL_2_OUT_0 … #define PCEP_RCTRL_2_OUT_0_MSG_CODE … #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x) … #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x) … #define PCEP_RCTRL_2_OUT_0_TAG … #define PCEP_RCTRL_2_OUT_0_TAG_SET(x) … #define PCEP_RCTRL_2_OUT_0_TAG_GET(x) … #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN … #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x) … #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x) … #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS … #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x) … #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x) … #define PCEP_RCTRL_2_OUT_0_SNP … #define PCEP_RCTRL_2_OUT_0_SNP_SET(x) … #define PCEP_RCTRL_2_OUT_0_SNP_GET(x) … #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD … #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x) … #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x) … #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN … #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x) … #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x) … #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE … #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x) … #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x) … #define PCEP_RCTRL_2_OUT_0_INVERT_MODE … #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x) … #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x) … #define PCEP_RCTRL_2_OUT_0_REGION_EN … #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x) … #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x) … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_LWR_OUT_0 … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x) … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x) … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x) … #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x) … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_UPR_OUT_0 … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_LIM_OUT_0 … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x) … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x) … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x) … #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x) … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_LWR_TGT_OUT_0 … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_UPR_TGT_OUT_0 … /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ #define PCEP_ADDR_UPR_LIM_OUT_0 … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x) … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x) … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x) … #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ #define PCS10G_BR_PCS_CFG(t) … #define PCS10G_BR_PCS_CFG_PCS_ENA … #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x) … #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x) … #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA … #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x) … #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x) … #define PCS10G_BR_PCS_CFG_SH_CNT_MAX … #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x) … #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x) … #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP … #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x) … #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x) … #define PCS10G_BR_PCS_CFG_RESYNC_ENA … #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x) … #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x) … #define PCS10G_BR_PCS_CFG_LF_GEN_DIS … #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x) … #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x) … #define PCS10G_BR_PCS_CFG_RX_TEST_MODE … #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x) … #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x) … #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE … #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x) … #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x) … #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP … #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x) … #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x) … #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA … #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x) … #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x) … #define PCS10G_BR_PCS_CFG_TX_TEST_MODE … #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x) … #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x) … #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE … #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x) … #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ #define PCS10G_BR_PCS_SD_CFG(t) … #define PCS10G_BR_PCS_SD_CFG_SD_SEL … #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x) … #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x) … #define PCS10G_BR_PCS_SD_CFG_SD_POL … #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x) … #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x) … #define PCS10G_BR_PCS_SD_CFG_SD_ENA … #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x) … #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ #define PCS25G_BR_PCS_CFG(t) … #define PCS25G_BR_PCS_CFG_PCS_ENA … #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x) … #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x) … #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA … #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x) … #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x) … #define PCS25G_BR_PCS_CFG_SH_CNT_MAX … #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x) … #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x) … #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP … #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x) … #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x) … #define PCS25G_BR_PCS_CFG_RESYNC_ENA … #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x) … #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x) … #define PCS25G_BR_PCS_CFG_LF_GEN_DIS … #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x) … #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x) … #define PCS25G_BR_PCS_CFG_RX_TEST_MODE … #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x) … #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x) … #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE … #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x) … #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x) … #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP … #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x) … #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x) … #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA … #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x) … #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x) … #define PCS25G_BR_PCS_CFG_TX_TEST_MODE … #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x) … #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x) … #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE … #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x) … #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ #define PCS25G_BR_PCS_SD_CFG(t) … #define PCS25G_BR_PCS_SD_CFG_SD_SEL … #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x) … #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x) … #define PCS25G_BR_PCS_SD_CFG_SD_POL … #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x) … #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x) … #define PCS25G_BR_PCS_SD_CFG_SD_ENA … #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x) … #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ #define PCS5G_BR_PCS_CFG(t) … #define PCS5G_BR_PCS_CFG_PCS_ENA … #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x) … #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x) … #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA … #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x) … #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x) … #define PCS5G_BR_PCS_CFG_SH_CNT_MAX … #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x) … #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x) … #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP … #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x) … #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x) … #define PCS5G_BR_PCS_CFG_RESYNC_ENA … #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x) … #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x) … #define PCS5G_BR_PCS_CFG_LF_GEN_DIS … #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x) … #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x) … #define PCS5G_BR_PCS_CFG_RX_TEST_MODE … #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x) … #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x) … #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE … #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x) … #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x) … #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP … #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x) … #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x) … #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA … #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x) … #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x) … #define PCS5G_BR_PCS_CFG_TX_TEST_MODE … #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x) … #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x) … #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE … #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x) … #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x) … /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ #define PCS5G_BR_PCS_SD_CFG(t) … #define PCS5G_BR_PCS_SD_CFG_SD_SEL … #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x) … #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x) … #define PCS5G_BR_PCS_SD_CFG_SD_POL … #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x) … #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x) … #define PCS5G_BR_PCS_SD_CFG_SD_ENA … #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x) … #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x) … /* PORT_CONF:HW_CFG:DEV5G_MODES */ #define PORT_CONF_DEV5G_MODES … #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE … #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x) … #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x) … /* PORT_CONF:HW_CFG:DEV10G_MODES */ #define PORT_CONF_DEV10G_MODES … #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE … #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x) … #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x) … /* PORT_CONF:HW_CFG:DEV25G_MODES */ #define PORT_CONF_DEV25G_MODES … #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE … #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x) … #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x) … /* PORT_CONF:HW_CFG:QSGMII_ENA */ #define PORT_CONF_QSGMII_ENA … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x) … #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x) … /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ #define PORT_CONF_USGMII_CFG(g) … #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM … #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x) … #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x) … #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM … #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x) … #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x) … #define PORT_CONF_USGMII_CFG_FLIP_LANES … #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x) … #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x) … #define PORT_CONF_USGMII_CFG_SHYST_DIS … #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x) … #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x) … #define PORT_CONF_USGMII_CFG_E_DET_ENA … #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x) … #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x) … #define PORT_CONF_USGMII_CFG_USE_I1_ENA … #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x) … #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x) … #define PORT_CONF_USGMII_CFG_QUAD_MODE … #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x) … #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x) … /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ #define PTP_PTP_PIN_INTR … #define PTP_PTP_PIN_INTR_INTR_PTP … #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x) … #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x) … /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ #define PTP_PTP_PIN_INTR_ENA … #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA … #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x) … #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x) … /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ #define PTP_PTP_INTR_IDENT … #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT … #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x) … #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x) … /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ #define PTP_PTP_DOM_CFG … #define PTP_PTP_DOM_CFG_PTP_ENA … #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x) … #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x) … #define PTP_PTP_DOM_CFG_PTP_HOLD … #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x) … #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x) … #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE … #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x) … #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x) … #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS … #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x) … #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ #define PTP_CLK_PER_CFG(g, r) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ #define PTP_PTP_CUR_NSEC(g) … #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC … #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x) … #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ #define PTP_PTP_CUR_NSEC_FRAC(g) … #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC … #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x) … #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ #define PTP_PTP_CUR_SEC_LSB(g) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ #define PTP_PTP_CUR_SEC_MSB(g) … #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB … #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x) … #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x) … /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ #define PTP_NTP_CUR_NSEC(g) … /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ #define PTP_PTP_PIN_CFG(g) … #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION … #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC … #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL … #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT … #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x) … #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT … #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x) … #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_DOM … #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_OPT … #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK … #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS … #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x) … #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x) … /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ #define PTP_PTP_TOD_SEC_MSB(g) … #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB … #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x) … #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x) … /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ #define PTP_PTP_TOD_SEC_LSB(g) … /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ #define PTP_PTP_TOD_NSEC(g) … #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC … #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x) … #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x) … /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ #define PTP_PTP_TOD_NSEC_FRAC(g) … #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC … #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x) … #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x) … /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ #define PTP_NTP_NSEC(g) … /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ #define PTP_PIN_WF_HIGH_PERIOD(g) … #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH … #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x) … #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x) … /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ #define PTP_PIN_WF_LOW_PERIOD(g) … #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL … #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x) … #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x) … /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ #define PTP_PIN_IOBOUNCH_DELAY(g) … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x) … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x) … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x) … #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x) … /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ #define PTP_PHAD_CTRL(g) … #define PTP_PHAD_CTRL_PHAD_ENA … #define PTP_PHAD_CTRL_PHAD_ENA_SET(x) … #define PTP_PHAD_CTRL_PHAD_ENA_GET(x) … #define PTP_PHAD_CTRL_PHAD_FAILED … #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x) … #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x) … #define PTP_PHAD_CTRL_REDUCED_RES … #define PTP_PHAD_CTRL_REDUCED_RES_SET(x) … #define PTP_PHAD_CTRL_REDUCED_RES_GET(x) … #define PTP_PHAD_CTRL_LOCK_ACC … #define PTP_PHAD_CTRL_LOCK_ACC_SET(x) … #define PTP_PHAD_CTRL_LOCK_ACC_GET(x) … /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ #define PTP_PHAD_CYC_STAT(g) … /* QFWD:SYSTEM:SWITCH_PORT_MODE */ #define QFWD_SWITCH_PORT_MODE(r) … #define QFWD_SWITCH_PORT_MODE_PORT_ENA … #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x) … #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x) … #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY … #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x) … #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x) … #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD … #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x) … #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x) … #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE … #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x) … #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x) … #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING … #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x) … #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x) … #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING … #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x) … #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x) … #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE … #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x) … #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x) … #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS … #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x) … #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x) … #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE … #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x) … #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x) … /* QFWD:SYSTEM:FRAME_COPY_CFG */ #define QFWD_FRAME_COPY_CFG(r) … #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL … #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x) … #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x) … /* QRES:RES_CTRL:RES_CFG */ #define QRES_RES_CFG(g) … #define QRES_RES_CFG_WM_HIGH … #define QRES_RES_CFG_WM_HIGH_SET(x) … #define QRES_RES_CFG_WM_HIGH_GET(x) … /* QRES:RES_CTRL:RES_STAT */ #define QRES_RES_STAT(g) … #define QRES_RES_STAT_MAXUSE … #define QRES_RES_STAT_MAXUSE_SET(x) … #define QRES_RES_STAT_MAXUSE_GET(x) … /* QRES:RES_CTRL:RES_STAT_CUR */ #define QRES_RES_STAT_CUR(g) … #define QRES_RES_STAT_CUR_INUSE … #define QRES_RES_STAT_CUR_INUSE_SET(x) … #define QRES_RES_STAT_CUR_INUSE_GET(x) … /* DEVCPU_QS:XTR:XTR_GRP_CFG */ #define QS_XTR_GRP_CFG(r) … #define QS_XTR_GRP_CFG_MODE … #define QS_XTR_GRP_CFG_MODE_SET(x) … #define QS_XTR_GRP_CFG_MODE_GET(x) … #define QS_XTR_GRP_CFG_STATUS_WORD_POS … #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x) … #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x) … #define QS_XTR_GRP_CFG_BYTE_SWAP … #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x) … #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x) … /* DEVCPU_QS:XTR:XTR_RD */ #define QS_XTR_RD(r) … /* DEVCPU_QS:XTR:XTR_FLUSH */ #define QS_XTR_FLUSH … #define QS_XTR_FLUSH_FLUSH … #define QS_XTR_FLUSH_FLUSH_SET(x) … #define QS_XTR_FLUSH_FLUSH_GET(x) … /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ #define QS_XTR_DATA_PRESENT … #define QS_XTR_DATA_PRESENT_DATA_PRESENT … #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x) … #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x) … /* DEVCPU_QS:INJ:INJ_GRP_CFG */ #define QS_INJ_GRP_CFG(r) … #define QS_INJ_GRP_CFG_MODE … #define QS_INJ_GRP_CFG_MODE_SET(x) … #define QS_INJ_GRP_CFG_MODE_GET(x) … #define QS_INJ_GRP_CFG_BYTE_SWAP … #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x) … #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x) … /* DEVCPU_QS:INJ:INJ_WR */ #define QS_INJ_WR(r) … /* DEVCPU_QS:INJ:INJ_CTRL */ #define QS_INJ_CTRL(r) … #define QS_INJ_CTRL_GAP_SIZE … #define QS_INJ_CTRL_GAP_SIZE_SET(x) … #define QS_INJ_CTRL_GAP_SIZE_GET(x) … #define QS_INJ_CTRL_ABORT … #define QS_INJ_CTRL_ABORT_SET(x) … #define QS_INJ_CTRL_ABORT_GET(x) … #define QS_INJ_CTRL_EOF … #define QS_INJ_CTRL_EOF_SET(x) … #define QS_INJ_CTRL_EOF_GET(x) … #define QS_INJ_CTRL_SOF … #define QS_INJ_CTRL_SOF_SET(x) … #define QS_INJ_CTRL_SOF_GET(x) … #define QS_INJ_CTRL_VLD_BYTES … #define QS_INJ_CTRL_VLD_BYTES_SET(x) … #define QS_INJ_CTRL_VLD_BYTES_GET(x) … /* DEVCPU_QS:INJ:INJ_STATUS */ #define QS_INJ_STATUS … #define QS_INJ_STATUS_WMARK_REACHED … #define QS_INJ_STATUS_WMARK_REACHED_SET(x) … #define QS_INJ_STATUS_WMARK_REACHED_GET(x) … #define QS_INJ_STATUS_FIFO_RDY … #define QS_INJ_STATUS_FIFO_RDY_SET(x) … #define QS_INJ_STATUS_FIFO_RDY_GET(x) … #define QS_INJ_STATUS_INJ_IN_PROGRESS … #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x) … #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x) … /* QSYS:PAUSE_CFG:PAUSE_CFG */ #define QSYS_PAUSE_CFG(r) … #define QSYS_PAUSE_CFG_PAUSE_START … #define QSYS_PAUSE_CFG_PAUSE_START_SET(x) … #define QSYS_PAUSE_CFG_PAUSE_START_GET(x) … #define QSYS_PAUSE_CFG_PAUSE_STOP … #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x) … #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x) … #define QSYS_PAUSE_CFG_PAUSE_ENA … #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x) … #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x) … #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA … #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x) … #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x) … /* QSYS:PAUSE_CFG:ATOP */ #define QSYS_ATOP(r) … #define QSYS_ATOP_ATOP … #define QSYS_ATOP_ATOP_SET(x) … #define QSYS_ATOP_ATOP_GET(x) … /* QSYS:PAUSE_CFG:FWD_PRESSURE */ #define QSYS_FWD_PRESSURE(r) … #define QSYS_FWD_PRESSURE_FWD_PRESSURE … #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x) … #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x) … #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS … #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x) … #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x) … /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ #define QSYS_ATOP_TOT_CFG … #define QSYS_ATOP_TOT_CFG_ATOP_TOT … #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x) … #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x) … /* QSYS:CALCFG:CAL_AUTO */ #define QSYS_CAL_AUTO(r) … #define QSYS_CAL_AUTO_CAL_AUTO … #define QSYS_CAL_AUTO_CAL_AUTO_SET(x) … #define QSYS_CAL_AUTO_CAL_AUTO_GET(x) … /* QSYS:CALCFG:CAL_CTRL */ #define QSYS_CAL_CTRL … #define QSYS_CAL_CTRL_CAL_MODE … #define QSYS_CAL_CTRL_CAL_MODE_SET(x) … #define QSYS_CAL_CTRL_CAL_MODE_GET(x) … #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE … #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x) … #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x) … #define QSYS_CAL_CTRL_CAL_AUTO_ERROR … #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x) … #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x) … /* QSYS:RAM_CTRL:RAM_INIT */ #define QSYS_RAM_INIT … #define QSYS_RAM_INIT_RAM_INIT … #define QSYS_RAM_INIT_RAM_INIT_SET(x) … #define QSYS_RAM_INIT_RAM_INIT_GET(x) … #define QSYS_RAM_INIT_RAM_CFG_HOOK … #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* REW:COMMON:OWN_UPSID */ #define REW_OWN_UPSID(r) … #define REW_OWN_UPSID_OWN_UPSID … #define REW_OWN_UPSID_OWN_UPSID_SET(x) … #define REW_OWN_UPSID_OWN_UPSID_GET(x) … /* REW:COMMON:RTAG_ETAG_CTRL */ #define REW_RTAG_ETAG_CTRL(r) … #define REW_RTAG_ETAG_CTRL_IPE_TBL … #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x) … #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x) … #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA … #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x) … #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x) … #define REW_RTAG_ETAG_CTRL_KEEP_ETAG … #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x) … #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x) … /* REW:COMMON:ES0_CTRL */ #define REW_ES0_CTRL … #define REW_ES0_CTRL_ES0_BY_RT_FWD … #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x) … #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x) … #define REW_ES0_CTRL_ES0_BY_RLEG … #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x) … #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x) … #define REW_ES0_CTRL_ES0_DPORT_ENA … #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x) … #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x) … #define REW_ES0_CTRL_ES0_FRM_LBK_CFG … #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x) … #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x) … #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA … #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x) … #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x) … #define REW_ES0_CTRL_ES0_LU_ENA … #define REW_ES0_CTRL_ES0_LU_ENA_SET(x) … #define REW_ES0_CTRL_ES0_LU_ENA_GET(x) … /* REW:PORT:PORT_VLAN_CFG */ #define REW_PORT_VLAN_CFG(g) … #define REW_PORT_VLAN_CFG_PORT_PCP … #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x) … #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x) … #define REW_PORT_VLAN_CFG_PORT_DEI … #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x) … #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x) … #define REW_PORT_VLAN_CFG_PORT_VID … #define REW_PORT_VLAN_CFG_PORT_VID_SET(x) … #define REW_PORT_VLAN_CFG_PORT_VID_GET(x) … /* REW:PORT:PCP_MAP_DE0 */ #define REW_PCP_MAP_DE0(g, r) … #define REW_PCP_MAP_DE0_PCP_DE0 … #define REW_PCP_MAP_DE0_PCP_DE0_SET(x) … #define REW_PCP_MAP_DE0_PCP_DE0_GET(x) … /* REW:PORT:PCP_MAP_DE1 */ #define REW_PCP_MAP_DE1(g, r) … #define REW_PCP_MAP_DE1_PCP_DE1 … #define REW_PCP_MAP_DE1_PCP_DE1_SET(x) … #define REW_PCP_MAP_DE1_PCP_DE1_GET(x) … /* REW:PORT:DEI_MAP_DE0 */ #define REW_DEI_MAP_DE0(g, r) … #define REW_DEI_MAP_DE0_DEI_DE0 … #define REW_DEI_MAP_DE0_DEI_DE0_SET(x) … #define REW_DEI_MAP_DE0_DEI_DE0_GET(x) … /* REW:PORT:DEI_MAP_DE1 */ #define REW_DEI_MAP_DE1(g, r) … #define REW_DEI_MAP_DE1_DEI_DE1 … #define REW_DEI_MAP_DE1_DEI_DE1_SET(x) … #define REW_DEI_MAP_DE1_DEI_DE1_GET(x) … /* REW:PORT:TAG_CTRL */ #define REW_TAG_CTRL(g) … #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED … #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x) … #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x) … #define REW_TAG_CTRL_TAG_CFG … #define REW_TAG_CTRL_TAG_CFG_SET(x) … #define REW_TAG_CTRL_TAG_CFG_GET(x) … #define REW_TAG_CTRL_TAG_TPID_CFG … #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x) … #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x) … #define REW_TAG_CTRL_TAG_VID_CFG … #define REW_TAG_CTRL_TAG_VID_CFG_SET(x) … #define REW_TAG_CTRL_TAG_VID_CFG_GET(x) … #define REW_TAG_CTRL_TAG_PCP_CFG … #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x) … #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x) … #define REW_TAG_CTRL_TAG_DEI_CFG … #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x) … #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x) … /* REW:PORT:DSCP_MAP */ #define REW_DSCP_MAP(g) … #define REW_DSCP_MAP_DSCP_UPDATE_ENA … #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x) … #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x) … #define REW_DSCP_MAP_DSCP_REMAP_ENA … #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x) … #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x) … /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ #define REW_PTP_TWOSTEP_CTRL … #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA … #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_NXT … #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_VLD … #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x) … #define REW_PTP_TWOSTEP_CTRL_STAMP_TX … #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x) … #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x) … #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT … #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x) … #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL … #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x) … #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x) … /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ #define REW_PTP_TWOSTEP_STAMP … #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC … #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x) … #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x) … /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ #define REW_PTP_TWOSTEP_STAMP_SUBNS … #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC … #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x) … #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x) … /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ #define REW_PTP_RSRV_NOT_ZERO … /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ #define REW_PTP_RSRV_NOT_ZERO1 … /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ #define REW_PTP_RSRV_NOT_ZERO2 … #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 … #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x) … #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x) … /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ #define REW_PTP_GEN_STAMP_FMT(r) … #define REW_PTP_GEN_STAMP_FMT_RT_OFS … #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x) … #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x) … #define REW_PTP_GEN_STAMP_FMT_RT_FMT … #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x) … #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x) … /* REW:RAM_CTRL:RAM_INIT */ #define REW_RAM_INIT … #define REW_RAM_INIT_RAM_INIT … #define REW_RAM_INIT_RAM_INIT_SET(x) … #define REW_RAM_INIT_RAM_INIT_GET(x) … #define REW_RAM_INIT_RAM_CFG_HOOK … #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ #define VCAP_ES0_CTRL … #define VCAP_ES0_CTRL_UPDATE_CMD … #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x) … #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x) … #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS … #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x) … #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x) … #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS … #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x) … #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x) … #define VCAP_ES0_CTRL_UPDATE_CNT_DIS … #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x) … #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x) … #define VCAP_ES0_CTRL_UPDATE_ADDR … #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x) … #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x) … #define VCAP_ES0_CTRL_UPDATE_SHOT … #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x) … #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x) … #define VCAP_ES0_CTRL_CLEAR_CACHE … #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x) … #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x) … #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN … #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x) … #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x) … /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ #define VCAP_ES0_CFG … #define VCAP_ES0_CFG_MV_NUM_POS … #define VCAP_ES0_CFG_MV_NUM_POS_SET(x) … #define VCAP_ES0_CFG_MV_NUM_POS_GET(x) … #define VCAP_ES0_CFG_MV_SIZE … #define VCAP_ES0_CFG_MV_SIZE_SET(x) … #define VCAP_ES0_CFG_MV_SIZE_GET(x) … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ #define VCAP_ES0_VCAP_ENTRY_DAT(r) … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ #define VCAP_ES0_VCAP_MASK_DAT(r) … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ #define VCAP_ES0_VCAP_ACTION_DAT(r) … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ #define VCAP_ES0_VCAP_CNT_DAT(r) … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ #define VCAP_ES0_VCAP_CNT_FW_DAT … /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ #define VCAP_ES0_VCAP_TG_DAT … /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ #define VCAP_ES0_IDX … #define VCAP_ES0_IDX_CORE_IDX … #define VCAP_ES0_IDX_CORE_IDX_SET(x) … #define VCAP_ES0_IDX_CORE_IDX_GET(x) … /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ #define VCAP_ES0_MAP … #define VCAP_ES0_MAP_CORE_MAP … #define VCAP_ES0_MAP_CORE_MAP_SET(x) … #define VCAP_ES0_MAP_CORE_MAP_GET(x) … /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ #define VCAP_ES0_VCAP_STICKY … #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY … #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x) … #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x) … /* VCAP_ES0:VCAP_CONST:VCAP_VER */ #define VCAP_ES0_VCAP_VER … /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ #define VCAP_ES0_ENTRY_WIDTH … /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ #define VCAP_ES0_ENTRY_CNT … /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ #define VCAP_ES0_ENTRY_SWCNT … /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ #define VCAP_ES0_ENTRY_TG_WIDTH … /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ #define VCAP_ES0_ACTION_DEF_CNT … /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ #define VCAP_ES0_ACTION_WIDTH … /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ #define VCAP_ES0_CNT_WIDTH … /* VCAP_ES0:VCAP_CONST:CORE_CNT */ #define VCAP_ES0_CORE_CNT … /* VCAP_ES0:VCAP_CONST:IF_CNT */ #define VCAP_ES0_IF_CNT … /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ #define VCAP_ES2_CTRL … #define VCAP_ES2_CTRL_UPDATE_CMD … #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x) … #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x) … #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS … #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x) … #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x) … #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS … #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x) … #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x) … #define VCAP_ES2_CTRL_UPDATE_CNT_DIS … #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x) … #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x) … #define VCAP_ES2_CTRL_UPDATE_ADDR … #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x) … #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x) … #define VCAP_ES2_CTRL_UPDATE_SHOT … #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x) … #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x) … #define VCAP_ES2_CTRL_CLEAR_CACHE … #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x) … #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x) … #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN … #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x) … #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x) … /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ #define VCAP_ES2_CFG … #define VCAP_ES2_CFG_MV_NUM_POS … #define VCAP_ES2_CFG_MV_NUM_POS_SET(x) … #define VCAP_ES2_CFG_MV_NUM_POS_GET(x) … #define VCAP_ES2_CFG_MV_SIZE … #define VCAP_ES2_CFG_MV_SIZE_SET(x) … #define VCAP_ES2_CFG_MV_SIZE_GET(x) … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ #define VCAP_ES2_VCAP_ENTRY_DAT(r) … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ #define VCAP_ES2_VCAP_MASK_DAT(r) … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ #define VCAP_ES2_VCAP_ACTION_DAT(r) … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ #define VCAP_ES2_VCAP_CNT_DAT(r) … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ #define VCAP_ES2_VCAP_CNT_FW_DAT … /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ #define VCAP_ES2_VCAP_TG_DAT … /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ #define VCAP_ES2_IDX … #define VCAP_ES2_IDX_CORE_IDX … #define VCAP_ES2_IDX_CORE_IDX_SET(x) … #define VCAP_ES2_IDX_CORE_IDX_GET(x) … /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ #define VCAP_ES2_MAP … #define VCAP_ES2_MAP_CORE_MAP … #define VCAP_ES2_MAP_CORE_MAP_SET(x) … #define VCAP_ES2_MAP_CORE_MAP_GET(x) … /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ #define VCAP_ES2_VCAP_STICKY … #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY … #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x) … #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x) … /* VCAP_ES2:VCAP_CONST:VCAP_VER */ #define VCAP_ES2_VCAP_VER … /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ #define VCAP_ES2_ENTRY_WIDTH … /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ #define VCAP_ES2_ENTRY_CNT … /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ #define VCAP_ES2_ENTRY_SWCNT … /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ #define VCAP_ES2_ENTRY_TG_WIDTH … /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ #define VCAP_ES2_ACTION_DEF_CNT … /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ #define VCAP_ES2_ACTION_WIDTH … /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ #define VCAP_ES2_CNT_WIDTH … /* VCAP_ES2:VCAP_CONST:CORE_CNT */ #define VCAP_ES2_CORE_CNT … /* VCAP_ES2:VCAP_CONST:IF_CNT */ #define VCAP_ES2_IF_CNT … /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ #define VCAP_SUPER_CTRL … #define VCAP_SUPER_CTRL_UPDATE_CMD … #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x) … #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS … #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x) … #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS … #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x) … #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS … #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x) … #define VCAP_SUPER_CTRL_UPDATE_ADDR … #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x) … #define VCAP_SUPER_CTRL_UPDATE_SHOT … #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x) … #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x) … #define VCAP_SUPER_CTRL_CLEAR_CACHE … #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x) … #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x) … #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN … #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x) … #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x) … /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ #define VCAP_SUPER_CFG … #define VCAP_SUPER_CFG_MV_NUM_POS … #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x) … #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x) … #define VCAP_SUPER_CFG_MV_SIZE … #define VCAP_SUPER_CFG_MV_SIZE_SET(x) … #define VCAP_SUPER_CFG_MV_SIZE_GET(x) … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ #define VCAP_SUPER_VCAP_ENTRY_DAT(r) … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ #define VCAP_SUPER_VCAP_MASK_DAT(r) … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ #define VCAP_SUPER_VCAP_ACTION_DAT(r) … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ #define VCAP_SUPER_VCAP_CNT_DAT(r) … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ #define VCAP_SUPER_VCAP_CNT_FW_DAT … /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ #define VCAP_SUPER_VCAP_TG_DAT … /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ #define VCAP_SUPER_IDX … #define VCAP_SUPER_IDX_CORE_IDX … #define VCAP_SUPER_IDX_CORE_IDX_SET(x) … #define VCAP_SUPER_IDX_CORE_IDX_GET(x) … /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ #define VCAP_SUPER_MAP … #define VCAP_SUPER_MAP_CORE_MAP … #define VCAP_SUPER_MAP_CORE_MAP_SET(x) … #define VCAP_SUPER_MAP_CORE_MAP_GET(x) … /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ #define VCAP_SUPER_VCAP_VER … /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ #define VCAP_SUPER_ENTRY_WIDTH … /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ #define VCAP_SUPER_ENTRY_CNT … /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ #define VCAP_SUPER_ENTRY_SWCNT … /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ #define VCAP_SUPER_ENTRY_TG_WIDTH … /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ #define VCAP_SUPER_ACTION_DEF_CNT … /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ #define VCAP_SUPER_ACTION_WIDTH … /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ #define VCAP_SUPER_CNT_WIDTH … /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ #define VCAP_SUPER_CORE_CNT … /* VCAP_SUPER:VCAP_CONST:IF_CNT */ #define VCAP_SUPER_IF_CNT … /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ #define VCAP_SUPER_RAM_INIT … #define VCAP_SUPER_RAM_INIT_RAM_INIT … #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x) … #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x) … #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK … #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* VOP:RAM_CTRL:RAM_INIT */ #define VOP_RAM_INIT … #define VOP_RAM_INIT_RAM_INIT … #define VOP_RAM_INIT_RAM_INIT_SET(x) … #define VOP_RAM_INIT_RAM_INIT_GET(x) … #define VOP_RAM_INIT_RAM_CFG_HOOK … #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x) … #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x) … /* XQS:SYSTEM:STAT_CFG */ #define XQS_STAT_CFG … #define XQS_STAT_CFG_STAT_CLEAR_SHOT … #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x) … #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x) … #define XQS_STAT_CFG_STAT_VIEW … #define XQS_STAT_CFG_STAT_VIEW_SET(x) … #define XQS_STAT_CFG_STAT_VIEW_GET(x) … #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY … #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x) … #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x) … #define XQS_STAT_CFG_STAT_WRAP_DIS … #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x) … #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x) … /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ #define XQS_QLIMIT_SHR_TOP_CFG(g) … #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP … #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x) … #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x) … /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ #define XQS_QLIMIT_SHR_ATOP_CFG(g) … #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP … #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x) … #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x) … /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ #define XQS_QLIMIT_SHR_CTOP_CFG(g) … #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP … #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x) … #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x) … /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ #define XQS_QLIMIT_SHR_QLIM_CFG(g) … #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM … #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x) … #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x) … /* XQS:STAT:CNT */ #define XQS_CNT(g) … #endif /* _SPARX5_MAIN_REGS_H_ */
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