/* SPDX-License-Identifier: GPL-2.0+ */ /* Microchip Sparx5 Switch driver * * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. */ #ifndef __SPARX5_MAIN_H__ #define __SPARX5_MAIN_H__ #include <linux/types.h> #include <linux/phy/phy.h> #include <linux/netdevice.h> #include <linux/phy.h> #include <linux/if_vlan.h> #include <linux/bitmap.h> #include <linux/phylink.h> #include <linux/net_tstamp.h> #include <linux/ptp_clock_kernel.h> #include <linux/hrtimer.h> #include <linux/debugfs.h> #include <net/flow_offload.h> #include "sparx5_main_regs.h" /* Target chip type */ enum spx5_target_chiptype { … }; enum sparx5_port_max_tags { … }; enum sparx5_vlan_port_type { … }; #define SPX5_PORTS … #define SPX5_PORT_CPU … #define SPX5_PORT_CPU_0 … #define SPX5_PORT_CPU_1 … #define SPX5_PORT_VD0 … #define SPX5_PORT_VD1 … #define SPX5_PORT_VD2 … #define SPX5_PORTS_ALL … #define PGID_BASE … #define PGID_UC_FLOOD … #define PGID_MC_FLOOD … #define PGID_IPV4_MC_DATA … #define PGID_IPV4_MC_CTRL … #define PGID_IPV6_MC_DATA … #define PGID_IPV6_MC_CTRL … #define PGID_BCAST … #define PGID_CPU … #define PGID_MCAST_START … #define PGID_TABLE_SIZE … #define IFH_LEN … #define NULL_VID … #define SPX5_MACT_PULL_DELAY … #define SPX5_STATS_CHECK_DELAY … #define SPX5_PRIOS … #define SPX5_BUFFER_CELL_SZ … #define SPX5_BUFFER_MEMORY … #define XTR_QUEUE … #define INJ_QUEUE … #define FDMA_DCB_MAX … #define FDMA_RX_DCB_MAX_DBS … #define FDMA_TX_DCB_MAX_DBS … #define SPARX5_PHC_COUNT … #define SPARX5_PHC_PORT … #define IFH_REW_OP_NOOP … #define IFH_REW_OP_ONE_STEP_PTP … #define IFH_REW_OP_TWO_STEP_PTP … #define IFH_PDU_TYPE_NONE … #define IFH_PDU_TYPE_PTP … #define IFH_PDU_TYPE_IPV4_UDP_PTP … #define IFH_PDU_TYPE_IPV6_UDP_PTP … struct sparx5; struct sparx5_db_hw { … }; struct sparx5_rx_dcb_hw { … }; struct sparx5_tx_dcb_hw { … }; /* Frame DMA receive state: * For each DB, there is a SKB, and the skb data pointer is mapped in * the DB. Once a frame is received the skb is given to the upper layers * and a new skb is added to the dcb. * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. */ struct sparx5_rx { … }; /* Frame DMA transmit state: * DCBs are chained using the DCBs nextptr field. */ struct sparx5_tx { … }; struct sparx5_port_config { … }; struct sparx5_port { … }; enum sparx5_core_clockfreq { … }; struct sparx5_phc { … }; struct sparx5_skb_cb { … }; struct sparx5_mdb_entry { … }; struct sparx5_mall_mirror_entry { … }; struct sparx5_mall_entry { … }; #define SPARX5_PTP_TIMEOUT … #define SPARX5_SKB_CB(skb) … struct sparx5 { … }; /* sparx5_switchdev.c */ int sparx5_register_notifier_blocks(struct sparx5 *sparx5); void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); /* sparx5_packet.c */ struct frame_info { … }; void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); irqreturn_t sparx5_xtr_handler(int irq, void *_priv); netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); int sparx5_manual_injection_mode(struct sparx5 *sparx5); void sparx5_port_inj_timer_setup(struct sparx5_port *port); /* sparx5_fdma.c */ int sparx5_fdma_start(struct sparx5 *sparx5); int sparx5_fdma_stop(struct sparx5 *sparx5); int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); irqreturn_t sparx5_fdma_handler(int irq, void *args); /* sparx5_mactable.c */ void sparx5_mact_pull_work(struct work_struct *work); int sparx5_mact_learn(struct sparx5 *sparx5, int port, const unsigned char mac[ETH_ALEN], u16 vid); bool sparx5_mact_getnext(struct sparx5 *sparx5, unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); int sparx5_mact_find(struct sparx5 *sparx5, const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); int sparx5_mact_forget(struct sparx5 *sparx5, const unsigned char mac[ETH_ALEN], u16 vid); int sparx5_add_mact_entry(struct sparx5 *sparx5, struct net_device *dev, u16 portno, const unsigned char *addr, u16 vid); int sparx5_del_mact_entry(struct sparx5 *sparx5, const unsigned char *addr, u16 vid); int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); void sparx5_mact_init(struct sparx5 *sparx5); /* sparx5_vlan.c */ void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); void sparx5_pgid_clear(struct sparx5 *spx5, int pgid); void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); void sparx5_update_fwd(struct sparx5 *sparx5); void sparx5_vlan_init(struct sparx5 *sparx5); void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, bool untagged); int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); /* sparx5_calendar.c */ int sparx5_config_auto_calendar(struct sparx5 *sparx5); int sparx5_config_dsm_calendar(struct sparx5 *sparx5); /* sparx5_ethtool.c */ void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); int sparx_stats_init(struct sparx5 *sparx5); /* sparx5_dcb.c */ #ifdef CONFIG_SPARX5_DCB int sparx5_dcb_init(struct sparx5 *sparx5); #else static inline int sparx5_dcb_init(struct sparx5 *sparx5) { return 0; } #endif /* sparx5_netdev.c */ void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); bool sparx5_netdevice_check(const struct net_device *dev); struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); int sparx5_register_netdevs(struct sparx5 *sparx5); void sparx5_destroy_netdevs(struct sparx5 *sparx5); void sparx5_unregister_netdevs(struct sparx5 *sparx5); /* sparx5_ptp.c */ int sparx5_ptp_init(struct sparx5 *sparx5); void sparx5_ptp_deinit(struct sparx5 *sparx5); int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct kernel_hwtstamp_config *cfg, struct netlink_ext_ack *extack); void sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct kernel_hwtstamp_config *cfg); void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, u64 timestamp); int sparx5_ptp_txtstamp_request(struct sparx5_port *port, struct sk_buff *skb); void sparx5_ptp_txtstamp_release(struct sparx5_port *port, struct sk_buff *skb); irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); /* sparx5_vcap_impl.c */ int sparx5_vcap_init(struct sparx5 *sparx5); void sparx5_vcap_destroy(struct sparx5 *sparx5); /* sparx5_pgid.c */ enum sparx5_pgid_type { … }; void sparx5_pgid_init(struct sparx5 *spx5); int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); /* sparx5_pool.c */ struct sparx5_pool_entry { … }; u32 sparx5_pool_idx_to_id(u32 idx); int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id); int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, u32 *id); /* sparx5_sdlb.c */ #define SPX5_SDLB_PUP_TOKEN_DISABLE … #define SPX5_SDLB_PUP_TOKEN_MAX … #define SPX5_SDLB_GROUP_RATE_MAX … #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET … #define SPX5_SDLB_CNT … #define SPX5_SDLB_GROUP_CNT … #define SPX5_CLK_PER_100PS_DEFAULT … struct sparx5_sdlb_group { … }; extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate); int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx); int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx); void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, u32 frame_size, u32 idx); /* sparx5_police.c */ enum { … }; struct sparx5_policer { … }; int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol); /* sparx5_psfp.c */ #define SPX5_PSFP_GCE_CNT … #define SPX5_PSFP_SG_CNT … #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS … #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS … #define SPX5_PSFP_SG_MAX_IPV … #define SPX5_PSFP_SG_OPEN … #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT … #define SPX5_PSFP_SF_MAX_SDU … struct sparx5_psfp_fm { … }; struct sparx5_psfp_gce { … }; struct sparx5_psfp_sg { … }; struct sparx5_psfp_sf { … }; int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, struct sparx5_psfp_fm *fm, u32 *id); int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id); int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, struct sparx5_psfp_sg *sg, u32 *id); int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id); int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, u32 *id); int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id); u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx); u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx); u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid); void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid); void sparx5_psfp_init(struct sparx5 *sparx5); /* sparx5_qos.c */ void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, const ktime_t org_base_time, ktime_t *new_base_time); /* sparx5_mirror.c */ int sparx5_mirror_add(struct sparx5_mall_entry *entry); void sparx5_mirror_del(struct sparx5_mall_entry *entry); void sparx5_mirror_stats(struct sparx5_mall_entry *entry, struct flow_stats *fstats); /* Clock period in picoseconds */ static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) { … } static inline bool sparx5_is_baser(phy_interface_t interface) { … } extern const struct phylink_mac_ops sparx5_phylink_mac_ops; extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; extern const struct ethtool_ops sparx5_ethtool_ops; extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops; /* Calculate raw offset */ static inline __pure int spx5_offset(int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } /* Read, Write and modify registers content. * The register definition macros start at the id */ static inline void __iomem *spx5_addr(void __iomem *base[], int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void __iomem *spx5_inst_addr(void __iomem *base, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void spx5_wr(u32 val, struct sparx5 *sparx5, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void spx5_inst_wr(u32 val, void __iomem *iomem, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) { … } static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, int id, int tinst, int tcnt, int gbase, int ginst, int gcnt, int gwidth, int raddr, int rinst, int rcnt, int rwidth) { … } #endif /* __SPARX5_MAIN_H__ */
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