/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */ /* Written/copyright 1999-2001 by Donald Becker. Portions copyright (c) 2001,2002 Sun Microsystems ([email protected]) Portions copyright 2001,2002 Manfred Spraul ([email protected]) Portions copyright 2004 Harald Welte <[email protected]> This software may be used and distributed according to the terms of the GNU General Public License (GPL), incorporated herein by reference. Drivers based on or derived from this code fall under the GPL and must retain the authorship, copyright and license notice. This file is not a complete program and may only be used when the entire operating system is licensed under the GPL. License for under other terms may be available. Contact the original author for details. The original author may be reached as [email protected], or at Scyld Computing Corporation 410 Severn Ave., Suite 210 Annapolis MD 21403 Support information and updates available at http://www.scyld.com/network/netsemi.html [link no longer provides useful info -jgarzik] TODO: * big endian support with CFG:BEM instead of cpu_to_le32 */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/timer.h> #include <linux/errno.h> #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/init.h> #include <linux/spinlock.h> #include <linux/ethtool.h> #include <linux/delay.h> #include <linux/rtnetlink.h> #include <linux/mii.h> #include <linux/crc32.h> #include <linux/bitops.h> #include <linux/prefetch.h> #include <asm/processor.h> /* Processor type for cache alignment. */ #include <asm/io.h> #include <asm/irq.h> #include <linux/uaccess.h> #define DRV_NAME … #define DRV_VERSION … #define DRV_RELDATE … #define RX_OFFSET … /* Updated to recommendations in pci-skeleton v2.03. */ /* The user-configurable values. These may be modified when a driver module is loaded.*/ #define NATSEMI_DEF_MSG … static int debug = …; static int mtu; /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). This chip uses a 512 element hash table based on the Ethernet CRC. */ static const int multicast_filter_limit = …; /* Set the copy breakpoint for the copy-only-tiny-frames scheme. Setting to > 1518 effectively disables this feature. */ static int rx_copybreak; static int dspcfg_workaround = …; /* Used to pass the media type, etc. Both 'options[]' and 'full_duplex[]' should exist for driver interoperability. The media type is usually passed in 'options[]'. */ #define MAX_UNITS … static int options[MAX_UNITS]; static int full_duplex[MAX_UNITS]; /* Operational parameters that are set at compile time. */ /* Keep the ring sizes a power of two for compile efficiency. The compiler will convert <unsigned>'%'<2^N> into a bit mask. Making the Tx ring too large decreases the effectiveness of channel bonding and packet priority. There are no ill effects from too-large receive rings. */ #define TX_RING_SIZE … #define TX_QUEUE_LEN … #define RX_RING_SIZE … /* Operational parameters that usually are not changed. */ /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT … #define NATSEMI_HW_TIMEOUT … #define NATSEMI_TIMER_FREQ … #define NATSEMI_PG0_NREGS … #define NATSEMI_RFDR_NREGS … #define NATSEMI_PG1_NREGS … #define NATSEMI_NREGS … #define NATSEMI_REGS_VER … #define NATSEMI_REGS_SIZE … /* Buffer sizes: * The nic writes 32-bit values, even if the upper bytes of * a 32-bit value are beyond the end of the buffer. */ #define NATSEMI_HEADERS … #define NATSEMI_PADDING … #define NATSEMI_LONGPKT … #define NATSEMI_RX_LIMIT … /* These identify the driver base version and may not be removed. */ static const char version[] = …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; module_param(mtu, int, 0); module_param(debug, int, 0); module_param(rx_copybreak, int, 0); module_param(dspcfg_workaround, int, 0); module_param_array(…); module_param_array(…); MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; MODULE_PARM_DESC(…) …; /* Theory of Operation I. Board Compatibility This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC. It also works with other chips in the DP83810 series. II. Board-specific settings This driver requires the PCI interrupt line to be valid. It honors the EEPROM-set values. III. Driver operation IIIa. Ring buffers This driver uses two statically allocated fixed-size descriptor lists formed into rings by a branch from the final descriptor to the beginning of the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. The NatSemi design uses a 'next descriptor' pointer that the driver forms into a list. IIIb/c. Transmit/Receive Structure This driver uses a zero-copy receive and transmit scheme. The driver allocates full frame size skbuffs for the Rx ring buffers at open() time and passes the skb->data field to the chip as receive data buffers. When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff is allocated and the frame is copied to the new skbuff. When the incoming frame is larger, the skbuff is passed directly up the protocol stack. Buffers consumed this way are replaced by newly allocated skbuffs in a later phase of receives. The RX_COPYBREAK value is chosen to trade-off the memory wasted by using a full-sized skbuff for small frames vs. the copying costs of larger frames. New boards are typically used in generously configured machines and the underfilled buffers have negligible impact compared to the benefit of a single allocation size, so the default value of zero results in never copying packets. When copying is done, the cost is usually mitigated by using a combined copy/checksum routine. Copying also preloads the cache, which is most useful with small frames. A subtle aspect of the operation is that unaligned buffers are not permitted by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't longword aligned for further processing. On copies frames are put into the skbuff at an offset of "+2", 16-byte aligning the IP header. IIId. Synchronization Most operations are synchronized on the np->lock irq spinlock, except the receive and transmit paths which are synchronised using a combination of hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. IVb. References http://www.scyld.com/expert/100mbps.html http://www.scyld.com/expert/NWay.html Datasheet is available from: http://www.national.com/pf/DP/DP83815.html IVc. Errata None characterised. */ /* * Support for fibre connections on Am79C874: * This phy needs a special setup when connected to a fibre cable. * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf */ #define PHYID_AM79C874 … enum { … }; enum { … }; /* array of board data directly indexed by pci_tbl[x].driver_data */ static struct { … } natsemi_pci_info[] = …; static const struct pci_device_id natsemi_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl); /* Offsets to the device registers. Unlike software-only systems, device drivers interact with complex hardware. It's not useful to define symbolic names for every register bit in the device. */ enum register_offsets { … }; /* the values for the 'magic' registers above (PGSEL=1) */ #define PMDCSR_VAL … #define TSTDAT_VAL … #define DSPCFG_VAL … #define SDCFG_VAL … #define DSPCFG_LOCK … #define DSPCFG_COEF … #define TSTDAT_FIXED … /* misc PCI space registers */ enum pci_register_offsets { … }; enum ChipCmd_bits { … }; enum ChipConfig_bits { … }; enum EECtrl_bits { … }; enum PCIBusCfg_bits { … }; /* Bits in the interrupt status/mask registers. */ enum IntrStatus_bits { … }; /* * Default Interrupts: * Rx OK, Rx Packet Error, Rx Overrun, * Tx OK, Tx Packet Error, Tx Underrun, * MIB Service, Phy Interrupt, High Bits, * Rx Status FIFO overrun, * Received Target Abort, Received Master Abort, * Signalled System Error, Received Parity Error */ #define DEFAULT_INTR … enum TxConfig_bits { … }; /* * Tx Configuration: * - 256 byte DMA burst length * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free) * - 64 bytes initial drain threshold (i.e. begin actual transmission * when 64 byte are in the fifo) * - on tx underruns, increase drain threshold by 64. * - at most use a drain threshold of 1472 bytes: The sum of the fill * threshold and the drain threshold must be less than 2016 bytes. * */ #define TX_FLTH_VAL … #define TX_DRTH_VAL_START … #define TX_DRTH_VAL_INC … #define TX_DRTH_VAL_LIMIT … enum RxConfig_bits { … }; #define RX_DRTH_VAL … enum ClkRun_bits { … }; enum WolCmd_bits { … }; enum RxFilterAddr_bits { … }; enum StatsCtrl_bits { … }; enum MIntrCtrl_bits { … }; enum PhyCtrl_bits { … }; #define PHY_ADDR_NONE … #define PHY_ADDR_INTERNAL … /* values we might find in the silicon revision register */ #define SRR_DP83815_C … #define SRR_DP83815_D … #define SRR_DP83816_A4 … #define SRR_DP83816_A5 … /* The Rx and Tx buffer descriptors. */ /* Note that using only 32 bit fields simplifies conversion to big-endian architectures. */ struct netdev_desc { … }; /* Bits in network_desc.status */ enum desc_status_bits { … }; struct netdev_private { … }; static void move_int_phy(struct net_device *dev, int addr); static int eeprom_read(void __iomem *ioaddr, int location); static int mdio_read(struct net_device *dev, int reg); static void mdio_write(struct net_device *dev, int reg, u16 data); static void init_phy_fixup(struct net_device *dev); static int miiport_read(struct net_device *dev, int phy_id, int reg); static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); static int find_mii(struct net_device *dev); static void natsemi_reset(struct net_device *dev); static void natsemi_reload_eeprom(struct net_device *dev); static void natsemi_stop_rxtx(struct net_device *dev); static int netdev_open(struct net_device *dev); static void do_cable_magic(struct net_device *dev); static void undo_cable_magic(struct net_device *dev); static void check_link(struct net_device *dev); static void netdev_timer(struct timer_list *t); static void dump_ring(struct net_device *dev); static void ns_tx_timeout(struct net_device *dev, unsigned int txqueue); static int alloc_ring(struct net_device *dev); static void refill_rx(struct net_device *dev); static void init_ring(struct net_device *dev); static void drain_tx(struct net_device *dev); static void drain_ring(struct net_device *dev); static void free_ring(struct net_device *dev); static void reinit_ring(struct net_device *dev); static void init_registers(struct net_device *dev); static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); static irqreturn_t intr_handler(int irq, void *dev_instance); static void netdev_error(struct net_device *dev, int intr_status); static int natsemi_poll(struct napi_struct *napi, int budget); static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do); static void netdev_tx_done(struct net_device *dev); static int natsemi_change_mtu(struct net_device *dev, int new_mtu); #ifdef CONFIG_NET_POLL_CONTROLLER static void natsemi_poll_controller(struct net_device *dev); #endif static void __set_rx_mode(struct net_device *dev); static void set_rx_mode(struct net_device *dev); static void __get_stats(struct net_device *dev); static struct net_device_stats *get_stats(struct net_device *dev); static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); static int netdev_set_wol(struct net_device *dev, u32 newval); static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur); static int netdev_set_sopass(struct net_device *dev, u8 *newval); static int netdev_get_sopass(struct net_device *dev, u8 *data); static int netdev_get_ecmd(struct net_device *dev, struct ethtool_link_ksettings *ecmd); static int netdev_set_ecmd(struct net_device *dev, const struct ethtool_link_ksettings *ecmd); static void enable_wol_mode(struct net_device *dev, int enable_intr); static int netdev_close(struct net_device *dev); static int netdev_get_regs(struct net_device *dev, u8 *buf); static int netdev_get_eeprom(struct net_device *dev, u8 *buf); static const struct ethtool_ops ethtool_ops; #define NATSEMI_ATTR(_name) … #define NATSEMI_CREATE_FILE(_dev, _name) … #define NATSEMI_REMOVE_FILE(_dev, _name) … NATSEMI_ATTR(…); static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t natsemi_set_dspcfg_workaround(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static inline void __iomem *ns_ioaddr(struct net_device *dev) { … } static inline void natsemi_irq_enable(struct net_device *dev) { … } static inline void natsemi_irq_disable(struct net_device *dev) { … } static void move_int_phy(struct net_device *dev, int addr) { … } static void natsemi_init_media(struct net_device *dev) { … } static const struct net_device_ops natsemi_netdev_ops = …; static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */ /* Delay between EEPROM clock transitions. No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that made udelay() unreliable. */ #define eeprom_delay(ee_addr) … #define EE_Write0 … #define EE_Write1 … /* The EEPROM commands include the alway-set leading bit. */ enum EEPROM_Cmds { … }; static int eeprom_read(void __iomem *addr, int location) { … } /* MII transceiver control section. * The 83815 series has an internal transceiver, and we present the * internal management registers as if they were MII connected. * External Phy registers are referenced through the MII interface. */ /* clock transitions >= 20ns (25MHz) * One readl should be good to PCI @ 100MHz */ #define mii_delay(ioaddr) … static int mii_getbit (struct net_device *dev) { … } static void mii_send_bits (struct net_device *dev, u32 data, int len) { … } static int miiport_read(struct net_device *dev, int phy_id, int reg) { … } static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) { … } static int mdio_read(struct net_device *dev, int reg) { … } static void mdio_write(struct net_device *dev, int reg, u16 data) { … } static void init_phy_fixup(struct net_device *dev) { … } static int switch_port_external(struct net_device *dev) { … } static int switch_port_internal(struct net_device *dev) { … } /* Scan for a PHY on the external mii bus. * There are two tricky points: * - Do not scan while the internal phy is enabled. The internal phy will * crash: e.g. reads from the DSPCFG register will return odd values and * the nasty random phy reset code will reset the nic every few seconds. * - The internal phy must be moved around, an external phy could * have the same address as the internal phy. */ static int find_mii(struct net_device *dev) { … } /* CFG bits [13:16] [18:23] */ #define CFG_RESET_SAVE … /* WCSR bits [0:4] [9:10] */ #define WCSR_RESET_SAVE … /* RFCR bits [20] [22] [27:31] */ #define RFCR_RESET_SAVE … static void natsemi_reset(struct net_device *dev) { … } static void reset_rx(struct net_device *dev) { … } static void natsemi_reload_eeprom(struct net_device *dev) { … } static void natsemi_stop_rxtx(struct net_device *dev) { … } static int netdev_open(struct net_device *dev) { … } static void do_cable_magic(struct net_device *dev) { … } static void undo_cable_magic(struct net_device *dev) { … } static void check_link(struct net_device *dev) { … } static void init_registers(struct net_device *dev) { … } /* * netdev_timer: * Purpose: * 1) check for link changes. Usually they are handled by the MII interrupt * but it doesn't hurt to check twice. * 2) check for sudden death of the NIC: * It seems that a reference set for this chip went out with incorrect info, * and there exist boards that aren't quite right. An unexpected voltage * drop can cause the PHY to get itself in a weird state (basically reset). * NOTE: this only seems to affect revC chips. The user can disable * this check via dspcfg_workaround sysfs option. * 3) check of death of the RX path due to OOM */ static void netdev_timer(struct timer_list *t) { … } static void dump_ring(struct net_device *dev) { … } static void ns_tx_timeout(struct net_device *dev, unsigned int txqueue) { … } static int alloc_ring(struct net_device *dev) { … } static void refill_rx(struct net_device *dev) { … } static void set_bufsize(struct net_device *dev) { … } /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ static void init_ring(struct net_device *dev) { … } static void drain_tx(struct net_device *dev) { … } static void drain_rx(struct net_device *dev) { … } static void drain_ring(struct net_device *dev) { … } static void free_ring(struct net_device *dev) { … } static void reinit_rx(struct net_device *dev) { … } static void reinit_ring(struct net_device *dev) { … } static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) { … } static void netdev_tx_done(struct net_device *dev) { … } /* The interrupt handler doesn't actually handle interrupts itself, it * schedules a NAPI poll if there is anything to do. */ static irqreturn_t intr_handler(int irq, void *dev_instance) { … } /* This is the NAPI poll routine. As well as the standard RX handling * it also handles all other interrupts that the chip might raise. */ static int natsemi_poll(struct napi_struct *napi, int budget) { … } /* This routine is logically part of the interrupt handler, but separated for clarity and better register allocation. */ static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do) { … } static void netdev_error(struct net_device *dev, int intr_status) { … } static void __get_stats(struct net_device *dev) { … } static struct net_device_stats *get_stats(struct net_device *dev) { … } #ifdef CONFIG_NET_POLL_CONTROLLER static void natsemi_poll_controller(struct net_device *dev) { … } #endif #define HASH_TABLE … static void __set_rx_mode(struct net_device *dev) { … } static int natsemi_change_mtu(struct net_device *dev, int new_mtu) { … } static void set_rx_mode(struct net_device *dev) { … } static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) { … } static int get_regs_len(struct net_device *dev) { … } static int get_eeprom_len(struct net_device *dev) { … } static int get_link_ksettings(struct net_device *dev, struct ethtool_link_ksettings *ecmd) { … } static int set_link_ksettings(struct net_device *dev, const struct ethtool_link_ksettings *ecmd) { … } static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) { … } static u32 get_msglevel(struct net_device *dev) { … } static void set_msglevel(struct net_device *dev, u32 val) { … } static int nway_reset(struct net_device *dev) { … } static u32 get_link(struct net_device *dev) { … } static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) { … } static const struct ethtool_ops ethtool_ops = …; static int netdev_set_wol(struct net_device *dev, u32 newval) { … } static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur) { … } static int netdev_set_sopass(struct net_device *dev, u8 *newval) { … } static int netdev_get_sopass(struct net_device *dev, u8 *data) { … } static int netdev_get_ecmd(struct net_device *dev, struct ethtool_link_ksettings *ecmd) { … } static int netdev_set_ecmd(struct net_device *dev, const struct ethtool_link_ksettings *ecmd) { … } static int netdev_get_regs(struct net_device *dev, u8 *buf) { … } #define SWAP_BITS(x) … static int netdev_get_eeprom(struct net_device *dev, u8 *buf) { … } static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { … } static void enable_wol_mode(struct net_device *dev, int enable_intr) { … } static int netdev_close(struct net_device *dev) { … } static void natsemi_remove1(struct pci_dev *pdev) { … } /* * The ns83815 chip doesn't have explicit RxStop bits. * Kicking the Rx or Tx process for a new packet reenables the Rx process * of the nic, thus this function must be very careful: * * suspend/resume synchronization: * entry points: * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler, * start_tx, ns_tx_timeout * * No function accesses the hardware without checking np->hands_off. * the check occurs under spin_lock_irq(&np->lock); * exceptions: * * netdev_ioctl: noncritical access. * * netdev_open: cannot happen due to the device_detach * * netdev_close: doesn't hurt. * * netdev_timer: timer stopped by natsemi_suspend. * * intr_handler: doesn't acquire the spinlock. suspend calls * disable_irq() to enforce synchronization. * * natsemi_poll: checks before reenabling interrupts. suspend * sets hands_off, disables interrupts and then waits with * napi_disable(). * * Interrupts must be disabled, otherwise hands_off can cause irq storms. */ static int __maybe_unused natsemi_suspend(struct device *dev_d) { … } static int __maybe_unused natsemi_resume(struct device *dev_d) { … } static SIMPLE_DEV_PM_OPS(natsemi_pm_ops, natsemi_suspend, natsemi_resume); static struct pci_driver natsemi_driver = …; static int __init natsemi_init_mod (void) { … } static void __exit natsemi_exit_mod (void) { … } module_init(…) …; module_exit(natsemi_exit_mod);
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