/************************************************************************ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2010 Exar Corp. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. ************************************************************************/ #include <linux/io-64-nonatomic-lo-hi.h> #ifndef _S2IO_H #define _S2IO_H #define TBD … #define s2BIT(loc) … #define vBIT(val, loc, sz) … #define INV(d) … #undef SUCCESS #define SUCCESS … #define FAILURE … #define S2IO_MINUS_ONE … #define S2IO_DISABLE_MAC_ENTRY … #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT … #define S2IO_BIT_RESET … #define S2IO_BIT_SET … #define CHECKBIT(value, nbit) … /* Maximum time to flicker LED when asked to identify NIC using ethtool */ #define MAX_FLICKER_TIME … /* Maximum outstanding splits to be configured into xena. */ enum { … }; #define XENA_MAX_OUTSTANDING_SPLITS(n) … /* OS concerned variables and constants */ #define WATCH_DOG_TIMEOUT … #define EFILL … #define ALIGN_SIZE … #define PCIX_COMMAND_REGISTER … /* * Debug related variables. */ /* different debug levels. */ #define ERR_DBG … #define INIT_DBG … #define INFO_DBG … #define TX_DBG … #define INTR_DBG … /* Global variable that defines the present debug level of the driver. */ static int debug_level = …; /* DEBUG message print. */ #define DBG_PRINT(dbg_level, fmt, args...) … /* Protocol assist features of the NIC */ #define L3_CKSUM_OK … #define L4_CKSUM_OK … #define S2IO_JUMBO_SIZE … /* Driver statistics maintained by driver */ struct swStat { … }; /* Xpak releated alarm and warnings */ struct xpakStat { … }; /* The statistics block of Xena */ struct stat_block { … }; /* Default value for 'vlan_strip_tag' configuration parameter */ #define NO_STRIP_IN_PROMISC … /* * Structures representing different init time configuration * parameters of the NIC. */ #define MAX_TX_FIFOS … #define MAX_RX_RINGS … #define FIFO_DEFAULT_NUM … #define FIFO_UDP_MAX_NUM … #define FIFO_OTHER_MAX_NUM … #define MAX_RX_DESC_1 … #define MAX_RX_DESC_2 … #define MAX_TX_DESC … /* FIFO mappings for all possible number of fifos configured */ static const int fifo_map[][MAX_TX_FIFOS] = …; static const u16 fifo_selector[MAX_TX_FIFOS] = …; /* Maintains Per FIFO related information. */ struct tx_fifo_config { … }; /* Maintains per Ring related information */ struct rx_ring_config { … }; /* This structure provides contains values of the tunable parameters * of the H/W */ struct config_param { … }; /* Structure representing MAC Addrs */ struct mac_addr { … }; /* Structure that represent every FIFO element in the BAR1 * Address location. */ struct TxFIFO_element { … }; /* Tx descriptor structure */ struct TxD { … }; /* Structure to hold the phy and virt addr of every TxDL. */ struct list_info_hold { … }; /* Rx descriptor structure for 1 buffer mode */ struct RxD_t { … }; /* Rx descriptor structure for 1 buffer mode */ struct RxD1 { … }; /* Rx descriptor structure for 3 or 2 buffer mode */ struct RxD3 { … }; /* Structure that represents the Rx descriptor block which contains * 128 Rx descriptors. */ struct RxD_block { … }; #define SIZE_OF_BLOCK … #define RXD_MODE_1 … #define RXD_MODE_3B … /* Structure to hold virtual addresses of Buf0 and Buf1 in * 2buf mode. */ struct buffAdd { … }; /* Structure which stores all the MAC control parameters */ /* This structure stores the offset of the RxD in the ring * from which the Rx Interrupt processor can start picking * up the RxDs for processing. */ struct rx_curr_get_info { … }; struct rx_curr_put_info { … }; /* This structure stores the offset of the TxDl in the FIFO * from which the Tx Interrupt processor can start picking * up the TxDLs for send complete interrupt processing. */ struct tx_curr_get_info { … }; struct tx_curr_put_info { … }; struct rxd_info { … }; /* Structure that holds the Phy and virt addresses of the Blocks */ struct rx_block_info { … }; /* Data structure to represent a LRO session */ struct lro { … } ____cacheline_aligned; /* Ring specific structure */ struct ring_info { … } ____cacheline_aligned; /* Fifo specific structure */ struct fifo_info { … } ____cacheline_aligned; /* Information related to the Tx and Rx FIFOs and Rings of Xena * is maintained in this structure. */ struct mac_info { … }; /* Default Tunable parameters of the NIC. */ #define DEFAULT_FIFO_0_LEN … #define DEFAULT_FIFO_1_7_LEN … #define SMALL_BLK_CNT … #define LARGE_BLK_CNT … /* * Structure to keep track of the MSI-X vectors and the corresponding * argument registered against each vector */ #define MAX_REQUESTED_MSI_X … struct s2io_msix_entry { … }; struct msix_info_st { … }; /* These flags represent the devices temporary state */ enum s2io_device_state_t { … }; /* Structure representing one instance of the NIC */ struct s2io_nic { … }; #define RESET_ERROR … #define CMD_ERROR … /* * Some registers have to be written in a particular order to * expect correct hardware operation. The macro SPECIAL_REG_WRITE * is used to perform such ordered writes. Defines UF (Upper First) * and LF (Lower First) will be used to specify the required write order. */ #define UF … #define LF … static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) { … } /* Interrupt related values of Xena */ #define ENABLE_INTRS … #define DISABLE_INTRS … /* Highest level interrupt blocks */ #define TX_PIC_INTR … #define TX_DMA_INTR … #define TX_MAC_INTR … #define TX_XGXS_INTR … #define TX_TRAFFIC_INTR … #define RX_PIC_INTR … #define RX_DMA_INTR … #define RX_MAC_INTR … #define RX_XGXS_INTR … #define RX_TRAFFIC_INTR … #define MC_INTR … #define ENA_ALL_INTRS … /* Interrupt masks for the general interrupt mask register */ #define DISABLE_ALL_INTRS … #define TXPIC_INT_M … #define TXDMA_INT_M … #define TXMAC_INT_M … #define TXXGXS_INT_M … #define TXTRAFFIC_INT_M … #define PIC_RX_INT_M … #define RXDMA_INT_M … #define RXMAC_INT_M … #define MC_INT_M … #define RXXGXS_INT_M … #define RXTRAFFIC_INT_M … /* PIC level Interrupts TODO*/ /* DMA level Inressupts */ #define TXDMA_PFC_INT_M … #define TXDMA_PCC_INT_M … /* PFC block interrupts */ #define PFC_MISC_ERR_1 … /* PCC block interrupts. */ #define PCC_FB_ECC_ERR … #define RXD_GET_VLAN_TAG(Control_2) … /* * Prototype declaration. */ static int s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre); static void s2io_rem_nic(struct pci_dev *pdev); static int init_shared_mem(struct s2io_nic *sp); static void free_shared_mem(struct s2io_nic *sp); static int init_nic(struct s2io_nic *nic); static int rx_intr_handler(struct ring_info *ring_data, int budget); static void s2io_txpic_intr_handle(struct s2io_nic *sp); static void tx_intr_handler(struct fifo_info *fifo_data); static void s2io_handle_errors(void * dev_id); static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue); static void s2io_set_multicast(struct net_device *dev, bool may_sleep); static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); static void s2io_link(struct s2io_nic * sp, int link); static void s2io_reset(struct s2io_nic * sp); static int s2io_poll_msix(struct napi_struct *napi, int budget); static int s2io_poll_inta(struct napi_struct *napi, int budget); static void s2io_init_pci(struct s2io_nic * sp); static int do_s2io_prog_unicast(struct net_device *dev, const u8 *addr); static void s2io_alarm_handle(struct timer_list *t); static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id); static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id); static irqreturn_t s2io_isr(int irq, void *dev_id); static int verify_xena_quiescence(struct s2io_nic *sp); static const struct ethtool_ops netdev_ethtool_ops; static void s2io_set_link(struct work_struct *work); static int s2io_set_swapper(struct s2io_nic * sp); static void s2io_card_down(struct s2io_nic *nic); static int s2io_card_up(struct s2io_nic *nic); static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, int bit_state, bool may_sleep); static int s2io_add_isr(struct s2io_nic * sp); static void s2io_rem_isr(struct s2io_nic * sp); static void restore_xmsi_data(struct s2io_nic *nic); static void do_s2io_store_unicast_mc(struct s2io_nic *sp); static void do_s2io_restore_unicast_mc(struct s2io_nic *sp); static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset); static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr); static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset); static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr); static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, struct s2io_nic *sp); static void clear_lro_session(struct lro *lro); static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag); static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, struct sk_buff *skb, u32 tcp_len); static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state); static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev); static void s2io_io_resume(struct pci_dev *pdev); #define s2io_tcp_mss(skb) … #define s2io_udp_mss(skb) … #define s2io_offload_type(skb) … #define S2IO_PARM_INT(X, def_val) … #endif /* _S2IO_H */
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