linux/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * QLogic qlcnic NIC Driver
 * Copyright (c) 2009-2013 QLogic Corporation
 */

#ifndef __QLCNIC_HDR_H_
#define __QLCNIC_HDR_H_

#include <linux/kernel.h>
#include <linux/types.h>

#include "qlcnic_hw.h"

/*
 * The basic unit of access when reading/writing control registers.
 */

enum {};

/*  Hub 0 */
enum {};

/*  Hub 1 */
enum {};

/*  Hub 2 */
enum {};

/*  Hub 3 */
enum {};

/*  Hub 4 */
enum {};

/*  Hub 5 */
enum {};

/*  Hub 6 */
enum {};

/*  Floaters - non existent modules */
#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR

/*  This field defines PCI/X adr [25:20] of agents on the CRB */
enum {};

#define BIT_0
#define BIT_1
#define BIT_2
#define BIT_3
#define BIT_4
#define BIT_5
#define BIT_6
#define BIT_7
#define BIT_8
#define BIT_9
#define BIT_10
#define BIT_11
#define BIT_12
#define BIT_13
#define BIT_14
#define BIT_15
#define BIT_16
#define BIT_17
#define BIT_18
#define BIT_19
#define BIT_20
#define BIT_21
#define BIT_22
#define BIT_23
#define BIT_24
#define BIT_25
#define BIT_26
#define BIT_27
#define BIT_28
#define BIT_29
#define BIT_30
#define BIT_31

/*  This field defines CRB adr [31:20] of the agents */

#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB

#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1

#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE
#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3

#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC

#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM
#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1
#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC

#define QLCNIC_SRE_MISC

#define QLCNIC_I2Q_CLR_PCI_HI

#define ROMUSB_GLB
#define ROMUSB_ROM

#define QLCNIC_ROMUSB_GLB_STATUS
#define QLCNIC_ROMUSB_GLB_SW_RESET
#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I
#define QLCNIC_ROMUSB_GLB_CAS_RST
#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL
#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE
#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL

#define QLCNIC_ROMUSB_GPIO(n)

#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE
#define QLCNIC_ROMUSB_ROM_ADDRESS
#define QLCNIC_ROMUSB_ROM_WDATA
#define QLCNIC_ROMUSB_ROM_ABYTE_CNT
#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT
#define QLCNIC_ROMUSB_ROM_RDATA

/******************************************************************************
*
*    Definitions specific to M25P flash
*
*******************************************************************************
*/

/* all are 1MB windows */

#define QLCNIC_PCI_CRB_WINDOWSIZE
#define QLCNIC_PCI_CRB_WINDOW(A)

#define QLCNIC_CRB_NIU
#define QLCNIC_CRB_SRE
#define QLCNIC_CRB_ROMUSB
#define QLCNIC_CRB_EPG
#define QLCNIC_CRB_I2Q
#define QLCNIC_CRB_TIMER
#define QLCNIC_CRB_I2C0
#define QLCNIC_CRB_SMB
#define QLCNIC_CRB_MAX

#define QLCNIC_CRB_PCIX_HOST
#define QLCNIC_CRB_PCIX_HOST2
#define QLCNIC_CRB_PEG_NET_0
#define QLCNIC_CRB_PEG_NET_1
#define QLCNIC_CRB_PEG_NET_2
#define QLCNIC_CRB_PEG_NET_3
#define QLCNIC_CRB_PEG_NET_4
#define QLCNIC_CRB_PEG_NET_D
#define QLCNIC_CRB_PEG_NET_I
#define QLCNIC_CRB_DDR_NET
#define QLCNIC_CRB_QDR_NET

#define QLCNIC_CRB_PCIX_MD
#define QLCNIC_CRB_PCIE

#define ISR_INT_VECTOR
#define ISR_INT_MASK
#define ISR_INT_MASK_SLOW
#define ISR_INT_TARGET_STATUS
#define ISR_INT_TARGET_MASK
#define ISR_INT_TARGET_STATUS_F1
#define ISR_INT_TARGET_MASK_F1
#define ISR_INT_TARGET_STATUS_F2
#define ISR_INT_TARGET_MASK_F2
#define ISR_INT_TARGET_STATUS_F3
#define ISR_INT_TARGET_MASK_F3
#define ISR_INT_TARGET_STATUS_F4
#define ISR_INT_TARGET_MASK_F4
#define ISR_INT_TARGET_STATUS_F5
#define ISR_INT_TARGET_MASK_F5
#define ISR_INT_TARGET_STATUS_F6
#define ISR_INT_TARGET_MASK_F6
#define ISR_INT_TARGET_STATUS_F7
#define ISR_INT_TARGET_MASK_F7

#define QLCNIC_PCI_OCM0_2M
#define QLCNIC_PCI_CRBSPACE
#define QLCNIC_PCI_CAMQM
#define QLCNIC_PCI_CAMQM_END
#define QLCNIC_PCI_CAMQM_2M_BASE

#define QLCNIC_CRB_CAM

#define QLCNIC_ADDR_DDR_NET
#define QLCNIC_ADDR_DDR_NET_MAX
#define QLCNIC_ADDR_OCM0
#define QLCNIC_ADDR_OCM0_MAX
#define QLCNIC_ADDR_OCM1
#define QLCNIC_ADDR_OCM1_MAX
#define QLCNIC_ADDR_QDR_NET
#define QLCNIC_ADDR_QDR_NET_MAX

/*
 *   Register offsets for MN
 */
#define QLCNIC_MIU_CONTROL
#define QLCNIC_MIU_MN_CONTROL

/* 200ms delay in each loop */
#define QLCNIC_NIU_PHY_WAITLEN
/* 10 seconds before we give up */
#define QLCNIC_NIU_PHY_WAITMAX
#define QLCNIC_NIU_MAX_GBE_PORTS
#define QLCNIC_NIU_MAX_XG_PORTS

#define QLCNIC_NIU_MODE
#define QLCNIC_NIU_GB_PAUSE_CTL
#define QLCNIC_NIU_XG_PAUSE_CTL

#define QLCNIC_NIU_GB_MAC_CONFIG_0(I)
#define QLCNIC_NIU_GB_MAC_CONFIG_1(I)

#define MAX_CTL_CHECK
#define TEST_AGT_CTRL

#define TA_CTL_START
#define TA_CTL_ENABLE
#define TA_CTL_WRITE
#define TA_CTL_BUSY

/* XG Link status */
#define XG_LINK_UP
#define XG_LINK_DOWN

#define XG_LINK_UP_P3P
#define XG_LINK_DOWN_P3P
#define XG_LINK_STATE_P3P_MASK
#define XG_LINK_STATE_P3P(pcifn, val)

#define P3P_LINK_SPEED_MHZ
#define P3P_LINK_SPEED_MASK
#define P3P_LINK_SPEED_REG(pcifn)
#define P3P_LINK_SPEED_VAL(pcifn, reg)

#define QLCNIC_CAM_RAM_BASE
#define QLCNIC_CAM_RAM(reg)
#define QLCNIC_ROM_LOCK_ID
#define QLCNIC_PHY_LOCK_ID
#define QLCNIC_CRB_WIN_LOCK_ID

#define NIC_CRB_BASE
#define NIC_CRB_BASE_2
#define QLCNIC_REG(X)
#define QLCNIC_REG_2(X)

#define QLCNIC_CDRP_MAX_ARGS
#define QLCNIC_CDRP_ARG(i)

#define QLCNIC_CDRP_CRB_OFFSET
#define QLCNIC_SIGN_CRB_OFFSET

#define CRB_XG_STATE_P3P
#define CRB_PF_LINK_SPEED_1
#define CRB_DRIVER_VERSION

#define CRB_FW_CAPABILITIES_2

/*
 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
 * which can be read by the Phantom host to get producer/consumer indexes from
 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
 * registers will be used for the addresses of the ring's shared memory
 * on the Phantom.
 */

#define qlcnic_get_temp_val(x)
#define qlcnic_get_temp_state(x)
#define qlcnic_encode_temp(val, state)

/*
 * Temperature control.
 */
enum {};


/* Lock IDs for PHY lock */
#define PHY_LOCK_DRIVER

#define PCIX_INT_VECTOR
#define PCIX_INT_MASK

#define PCIX_OCM_WINDOW
#define PCIX_OCM_WINDOW_REG(func)

#define PCIX_TARGET_STATUS
#define PCIX_TARGET_STATUS_F1
#define PCIX_TARGET_STATUS_F2
#define PCIX_TARGET_STATUS_F3
#define PCIX_TARGET_STATUS_F4
#define PCIX_TARGET_STATUS_F5
#define PCIX_TARGET_STATUS_F6
#define PCIX_TARGET_STATUS_F7

#define PCIX_TARGET_MASK
#define PCIX_TARGET_MASK_F1
#define PCIX_TARGET_MASK_F2
#define PCIX_TARGET_MASK_F3
#define PCIX_TARGET_MASK_F4
#define PCIX_TARGET_MASK_F5
#define PCIX_TARGET_MASK_F6
#define PCIX_TARGET_MASK_F7

#define PCIX_MSI_F(i)

#define QLCNIC_PCIX_PH_REG(reg)
#define QLCNIC_PCIX_PS_REG(reg)
#define QLCNIC_PCIE_REG(reg)

#define PCIE_SEM0_LOCK
#define PCIE_SEM0_UNLOCK
#define PCIE_SEM_LOCK(N)
#define PCIE_SEM_UNLOCK(N)

#define PCIE_SETUP_FUNCTION
#define PCIE_SETUP_FUNCTION2
#define PCIE_MISCCFG_RC
#define PCIE_TGT_SPLIT_CHICKEN
#define PCIE_CHICKEN3

#define ISR_INT_STATE_REG
#define PCIE_MAX_MASTER_SPLIT

#define QLCNIC_PORT_MODE_NONE
#define QLCNIC_PORT_MODE_XG
#define QLCNIC_PORT_MODE_GB
#define QLCNIC_PORT_MODE_802_3_AP
#define QLCNIC_PORT_MODE_AUTO_NEG
#define QLCNIC_PORT_MODE_AUTO_NEG_1G
#define QLCNIC_PORT_MODE_AUTO_NEG_XG
#define QLCNIC_PORT_MODE_ADDR
#define QLCNIC_WOL_PORT_MODE

#define QLCNIC_WOL_CONFIG_NV
#define QLCNIC_WOL_CONFIG

#define QLCNIC_PEG_TUNE_MN_PRESENT
#define QLCNIC_PEG_TUNE_CAPABILITY

#define QLCNIC_DMA_WATCHDOG_CTRL
#define QLCNIC_ROM_DEV_INIT_TIMEOUT
#define QLCNIC_ROM_DRV_RESET_TIMEOUT

/* Device State */
#define QLCNIC_DEV_COLD
#define QLCNIC_DEV_INITIALIZING
#define QLCNIC_DEV_READY
#define QLCNIC_DEV_NEED_RESET
#define QLCNIC_DEV_NEED_QUISCENT
#define QLCNIC_DEV_FAILED
#define QLCNIC_DEV_QUISCENT

#define QLCNIC_DEV_BADBAD

#define QLCNIC_DEV_NPAR_NON_OPER
#define QLCNIC_DEV_NPAR_OPER
#define QLCNIC_DEV_NPAR_OPER_TIMEO

#define QLC_DEV_SET_REF_CNT(VAL, FN)
#define QLC_DEV_CLR_REF_CNT(VAL, FN)
#define QLC_DEV_SET_RST_RDY(VAL, FN)
#define QLC_DEV_SET_QSCNT_RDY(VAL, FN)
#define QLC_DEV_CLR_RST_QSCNT(VAL, FN)

#define QLC_DEV_GET_DRV(VAL, FN)
#define QLC_DEV_SET_DRV(VAL, FN)

#define QLCNIC_TYPE_NIC
#define QLCNIC_TYPE_FCOE
#define QLCNIC_TYPE_ISCSI

#define QLCNIC_RCODE_DRIVER_INFO
#define QLCNIC_RCODE_DRIVER_CAN_RELOAD
#define QLCNIC_RCODE_FATAL_ERROR
#define QLCNIC_FWERROR_PEGNUM(code)
#define QLCNIC_FWERROR_CODE(code)
#define QLCNIC_FWERROR_FAN_FAILURE

#define FW_POLL_DELAY
#define FW_FAIL_THRESH

#define QLCNIC_RESET_TIMEOUT_SECS
#define QLCNIC_INIT_TIMEOUT_SECS
#define QLCNIC_RCVPEG_CHECK_RETRY_COUNT
#define QLCNIC_RCVPEG_CHECK_DELAY
#define QLCNIC_CMDPEG_CHECK_RETRY_COUNT
#define QLCNIC_CMDPEG_CHECK_DELAY
#define QLCNIC_HEARTBEAT_PERIOD_MSECS
#define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT

#define QLCNIC_MAX_MC_COUNT
#define QLCNIC_MAX_UC_COUNT
#define QLCNIC_WATCHDOG_TIMEOUTVALUE

#define ISR_MSI_INT_TRIGGER(FUNC)
#define ISR_LEGACY_INT_TRIGGERED(VAL)

/*
 * PCI Interrupt Vector Values.
 */
#define PCIX_INT_VECTOR_BIT_F0
#define PCIX_INT_VECTOR_BIT_F1
#define PCIX_INT_VECTOR_BIT_F2
#define PCIX_INT_VECTOR_BIT_F3
#define PCIX_INT_VECTOR_BIT_F4
#define PCIX_INT_VECTOR_BIT_F5
#define PCIX_INT_VECTOR_BIT_F6
#define PCIX_INT_VECTOR_BIT_F7

struct qlcnic_legacy_intr_set {};

#define QLCNIC_MSIX_BASE
#define QLCNIC_MAX_VLAN_FILTERS

#define FLASH_ROM_WINDOW
#define FLASH_ROM_DATA

#define QLCNIC_FW_DUMP_REG1
#define QLCNIC_FW_DUMP_REG2
#define QLCNIC_FLASH_SEM2_LK
#define QLCNIC_FLASH_SEM2_ULK
#define QLCNIC_FLASH_LOCK_ID

/* PCI function operational mode */
enum {};

enum {};

#define QLC_DEV_DRV_DEFAULT

#define LSB(x)
#define MSB(x)

#define LSW(x)
#define MSW(x)

#define LSD(x)
#define MSD(x)

#define QLCNIC_MS_CTRL
#define QLCNIC_MS_ADDR_LO
#define QLCNIC_MS_ADDR_HI
#define QLCNIC_MS_WRTDATA_LO
#define QLCNIC_MS_WRTDATA_HI
#define QLCNIC_MS_WRTDATA_ULO
#define QLCNIC_MS_WRTDATA_UHI
#define QLCNIC_MS_RDDATA_LO
#define QLCNIC_MS_RDDATA_HI
#define QLCNIC_MS_RDDATA_ULO
#define QLCNIC_MS_RDDATA_UHI

#define QLCNIC_TA_WRITE_ENABLE
#define QLCNIC_TA_WRITE_START
#define QLCNIC_TA_START_ENABLE

#define QLCNIC_LEGACY_INTR_CONFIG

/* NIU REGS */

#define _qlcnic_crb_get_bit(var, bit)

/*
 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
 *
 *	Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
 *	Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
 *	Bit 2 : enable_rx => 1:enable frame recv, 0:disable
 *	Bit 3 : rx_synced => R/O: recv enable synched to recv stream
 *	Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
 *	Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
 *	Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
 *	Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
 *	Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
 *	Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
 *	Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
 *	Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
 */
#define qlcnic_gb_rx_flowctl(config_word)
#define qlcnic_gb_get_rx_flowctl(config_word)
#define qlcnic_gb_unset_rx_flowctl(config_word)

/*
 * NIU GB Pause Ctl Register
 */

#define qlcnic_gb_set_gb0_mask(config_word)
#define qlcnic_gb_set_gb1_mask(config_word)
#define qlcnic_gb_set_gb2_mask(config_word)
#define qlcnic_gb_set_gb3_mask(config_word)

#define qlcnic_gb_get_gb0_mask(config_word)
#define qlcnic_gb_get_gb1_mask(config_word)
#define qlcnic_gb_get_gb2_mask(config_word)
#define qlcnic_gb_get_gb3_mask(config_word)

#define qlcnic_gb_unset_gb0_mask(config_word)
#define qlcnic_gb_unset_gb1_mask(config_word)
#define qlcnic_gb_unset_gb2_mask(config_word)
#define qlcnic_gb_unset_gb3_mask(config_word)

/*
 * NIU XG Pause Ctl Register
 *
 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 *      Bit 1       : xg0_request => 1:request single pause frame
 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 *      Bit 4       : xg1_request => 1:request single pause frame
 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 */

#define qlcnic_xg_set_xg0_mask(config_word)
#define qlcnic_xg_set_xg1_mask(config_word)

#define qlcnic_xg_get_xg0_mask(config_word)
#define qlcnic_xg_get_xg1_mask(config_word)

#define qlcnic_xg_unset_xg0_mask(config_word)
#define qlcnic_xg_unset_xg1_mask(config_word)

/*
 * NIU XG Pause Ctl Register
 *
 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 *      Bit 1       : xg0_request => 1:request single pause frame
 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 *      Bit 4       : xg1_request => 1:request single pause frame
 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 */

/*
 * PHY-Specific MII control/status registers.
 */
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS

/*
 * PHY-Specific Status Register (reg 17).
 *
 * Bit 0      : jabber => 1:jabber detected, 0:not
 * Bit 1      : polarity => 1:polarity reversed, 0:normal
 * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
 * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
 * Bit 4      : energydetect => 1:sleep, 0:active
 * Bit 5      : downshift => 1:downshift, 0:no downshift
 * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
 * Bits 7-9   : cablelen => not valid in 10Mb/s mode
 *			0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
 * Bit 10     : link => 1:link up, 0:link down
 * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
 * Bit 12     : pagercvd => 1:page received, 0:page not received
 * Bit 13     : duplex => 1:full duplex, 0:half duplex
 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
 */

#define qlcnic_get_phy_speed(config_word)

#define qlcnic_set_phy_speed(config_word, val)
#define qlcnic_set_phy_duplex(config_word)
#define qlcnic_clear_phy_duplex(config_word)

#define qlcnic_get_phy_link(config_word)
#define qlcnic_get_phy_duplex(config_word)

#define QLCNIC_NIU_NON_PROMISC_MODE
#define QLCNIC_NIU_PROMISC_MODE
#define QLCNIC_NIU_ALLMULTI_MODE

#define QLCNIC_PCIE_SEM_TIMEOUT

struct crb_128M_2M_sub_block_map {};

struct crb_128M_2M_block_map{};
#endif				/* __QLCNIC_HDR_H_ */