/* SPDX-License-Identifier: GPL-2.0-only */ /* * QLogic qlcnic NIC Driver * Copyright (c) 2009-2013 QLogic Corporation */ #ifndef __QLCNIC_83XX_HW_H #define __QLCNIC_83XX_HW_H #include <linux/types.h> #include <linux/etherdevice.h> #include "qlcnic_hw.h" #define QLCNIC_83XX_BAR0_LENGTH … /* Directly mapped registers */ #define QLC_83XX_CRB_WIN_BASE … #define QLC_83XX_CRB_WIN_FUNC(f) … #define QLC_83XX_SEM_LOCK_BASE … #define QLC_83XX_SEM_UNLOCK_BASE … #define QLC_83XX_SEM_LOCK_FUNC(f) … #define QLC_83XX_SEM_UNLOCK_FUNC(f) … #define QLC_83XX_LINK_STATE(f) … #define QLC_83XX_LINK_SPEED(f) … #define QLC_83XX_LINK_SPEED_FACTOR … #define QLC_83xx_FUNC_VAL(v, f) … #define QLC_83XX_INTX_PTR … #define QLC_83XX_INTX_TRGR … #define QLC_83XX_INTX_MASK … #define QLC_83XX_DRV_LOCK_WAIT_COUNTER … #define QLC_83XX_DRV_LOCK_WAIT_DELAY … #define QLC_83XX_NEED_DRV_LOCK_RECOVERY … #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS … #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT … #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY … #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK … #define QLC_83XX_LB_WAIT_COUNT … #define QLC_83XX_LB_MSLEEP_COUNT … #define QLC_83XX_NO_NIC_RESOURCE … #define QLC_83XX_MAC_PRESENT … #define QLC_83XX_MAC_ABSENT … #define QLC_83XX_FLASH_SECTOR_SIZE … /* PEG status definitions */ #define QLC_83XX_CMDPEG_COMPLETE … #define QLC_83XX_VALID_INTX_BIT30(val) … #define QLC_83XX_VALID_INTX_BIT31(val) … #define QLC_83XX_INTX_FUNC(val) … #define QLC_83XX_LEGACY_INTX_MAX_RETRY … #define QLC_83XX_LEGACY_INTX_DELAY … #define QLC_83XX_REG_DESC … #define QLC_83XX_LRO_DESC … #define QLC_83XX_CTRL_DESC … #define QLC_83XX_FW_CAPABILITY_TSO … #define QLC_83XX_FW_CAP_LRO_MSS … #define QLC_83XX_HOST_RDS_MODE_UNIQUE … #define QLC_83XX_HOST_SDS_MBX_IDX … #define QLCNIC_HOST_RDS_MBX_IDX … /* Pause control registers */ #define QLC_83XX_SRE_SHIM_REG … #define QLC_83XX_PORT0_THRESHOLD … #define QLC_83XX_PORT1_THRESHOLD … #define QLC_83XX_PORT0_TC_MC_REG … #define QLC_83XX_PORT1_TC_MC_REG … #define QLC_83XX_PORT0_TC_STATS … #define QLC_83XX_PORT1_TC_STATS … #define QLC_83XX_PORT2_IFB_THRESHOLD … #define QLC_83XX_PORT3_IFB_THRESHOLD … /* Peg PC status registers */ #define QLC_83XX_CRB_PEG_NET_0 … #define QLC_83XX_CRB_PEG_NET_1 … #define QLC_83XX_CRB_PEG_NET_2 … #define QLC_83XX_CRB_PEG_NET_3 … #define QLC_83XX_CRB_PEG_NET_4 … /* Firmware image definitions */ #define QLC_83XX_BOOTLOADER_FLASH_ADDR … #define QLC_83XX_FW_FILE_NAME … #define QLC_83XX_POST_FW_FILE_NAME … #define QLC_84XX_FW_FILE_NAME … #define QLC_83XX_BOOT_FROM_FLASH … #define QLC_83XX_BOOT_FROM_FILE … #define QLC_FW_FILE_NAME_LEN … #define QLC_83XX_MAX_RESET_SEQ_ENTRIES … #define QLC_83XX_MBX_POST_BC_OP … #define QLC_83XX_MBX_COMPLETION … #define QLC_83XX_MBX_REQUEST … #define QLC_83XX_MBX_TIMEOUT … #define QLC_83XX_MBX_CMD_LOOP … /* status descriptor mailbox data * @phy_addr_{low|high}: physical address of buffer * @sds_ring_size: buffer size * @intrpt_id: interrupt id * @intrpt_val: source of interrupt */ struct qlcnic_sds_mbx { … } __packed; /* receive descriptor buffer data * phy_addr_reg_{low|high}: physical address of regular buffer * phy_addr_jmb_{low|high}: physical address of jumbo buffer * reg_ring_sz: size of regular buffer * reg_ring_len: no. of entries in regular buffer * jmb_ring_len: no. of entries in jumbo buffer * jmb_ring_sz: size of jumbo buffer */ struct qlcnic_rds_mbx { … } __packed; /* host producers for regular and jumbo rings */ struct __host_producer_mbx { … } __packed; /* Receive context mailbox data outbox registers * @state: state of the context * @vport_id: virtual port id * @context_id: receive context id * @num_pci_func: number of pci functions of the port * @phy_port: physical port id */ struct qlcnic_rcv_mbx_out { … } __packed; struct qlcnic_add_rings_mbx_out { … } __packed; /* Transmit context mailbox inbox registers * @phys_addr_{low|high}: DMA address of the transmit buffer * @cnsmr_index_{low|high}: host consumer index * @size: legth of transmit buffer ring * @intr_id: interrupt id * @src: src of interrupt */ struct qlcnic_tx_mbx { … } __packed; /* Transmit context mailbox outbox registers * @host_prod: host producer index * @ctx_id: transmit context id * @state: state of the transmit context */ struct qlcnic_tx_mbx_out { … } __packed; struct qlcnic_intrpt_config { … }; struct qlcnic_macvlan_mbx { … }; struct qlc_83xx_fw_info { … }; struct qlc_83xx_reset { … }; #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY … #define QLC_83XX_IDC_GRACEFULL_RESET … #define QLC_83XX_IDC_DISABLE_FW_DUMP … #define QLC_83XX_IDC_TIMESTAMP … #define QLC_83XX_IDC_DURATION … #define QLC_83XX_IDC_INIT_TIMEOUT_SECS … #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS … #define QLC_83XX_IDC_RESET_TIMEOUT_SECS … #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS … #define QLC_83XX_IDC_FW_POLL_DELAY … #define QLC_83XX_IDC_FW_FAIL_THRESH … #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO … #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS … #define QLC_83XX_IDC_MAJOR_VERSION … #define QLC_83XX_IDC_MINOR_VERSION … #define QLC_83XX_IDC_FLASH_PARAM_ADDR … struct qlcnic_adapter; struct qlcnic_fw_dump; struct qlc_83xx_idc { … }; enum qlcnic_vlan_operations { … }; /* Device States */ enum qlcnic_83xx_states { … }; #define QLCNIC_MBX_RSP(reg) … #define QLCNIC_MBX_NUM_REGS(reg) … #define QLCNIC_MBX_STATUS(reg) … #define QLCNIC_MBX_HOST(ahw, i) … #define QLCNIC_MBX_FW(ahw, i) … /* Mailbox process AEN count */ #define QLC_83XX_IDC_COMP_AEN … #define QLC_83XX_MBX_AEN_CNT … #define QLC_83XX_MODULE_LOADED … #define QLC_83XX_MBX_READY … #define QLC_83XX_MBX_AEN_ACK … #define QLC_83XX_SFP_PRESENT(data) … #define QLC_83XX_SFP_ERR(data) … #define QLC_83XX_SFP_MODULE_TYPE(data) … #define QLC_83XX_SFP_CU_LENGTH(data) … #define QLC_83XX_SFP_TX_FAULT(data) … #define QLC_83XX_LINK_STATS(data) … #define QLC_83XX_CURRENT_LINK_SPEED(data) … #define QLC_83XX_LINK_PAUSE(data) … #define QLC_83XX_LINK_LB(data) … #define QLC_83XX_LINK_FEC(data) … #define QLC_83XX_LINK_EEE(data) … #define QLC_83XX_DCBX(data) … #define QLC_83XX_AUTONEG(data) … #define QLC_83XX_TX_PAUSE … #define QLC_83XX_RX_PAUSE … #define QLC_83XX_TX_RX_PAUSE … #define QLC_83XX_CFG_STD_PAUSE … #define QLC_83XX_CFG_STD_TX_PAUSE … #define QLC_83XX_CFG_STD_RX_PAUSE … #define QLC_83XX_CFG_STD_TX_RX_PAUSE … #define QLC_83XX_ENABLE_AUTONEG … #define QLC_83XX_CFG_LOOPBACK_HSS … #define QLC_83XX_CFG_LOOPBACK_PHY … #define QLC_83XX_CFG_LOOPBACK_EXT … /* LED configuration settings */ #define QLC_83XX_ENABLE_BEACON … #define QLC_83XX_BEACON_ON … #define QLC_83XX_BEACON_OFF … #define QLC_83XX_LED_RATE … #define QLC_83XX_LED_ACT … #define QLC_83XX_LED_MOD … #define QLC_83XX_LED_CONFIG … #define QLC_83XX_10M_LINK … #define QLC_83XX_100M_LINK … #define QLC_83XX_1G_LINK … #define QLC_83XX_10G_LINK … #define QLC_83XX_STAT_TX … #define QLC_83XX_STAT_RX … #define QLC_83XX_STAT_MAC … #define QLC_83XX_TX_STAT_REGS … #define QLC_83XX_RX_STAT_REGS … #define QLC_83XX_MAC_STAT_REGS … #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) … #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) … #define QLC_83XX_DEFAULT_OPMODE … #define QLC_83XX_PRIVLEGED_FUNC … #define QLC_83XX_VIRTUAL_FUNC … #define QLC_83XX_LB_MAX_FILTERS … #define QLC_83XX_LB_BUCKET_SIZE … #define QLC_83XX_MINIMUM_VECTOR … #define QLC_83XX_MAX_MC_COUNT … #define QLC_83XX_MAX_UC_COUNT … #define QLC_83XX_PVID_STRIP_CAPABILITY … #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) … #define QLC_83XX_GET_LRO_CAPABILITY(val) … #define QLC_83XX_GET_LSO_CAPABILITY(val) … #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) … #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) … #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) … #define QLC_83XX_ESWITCH_CAPABILITY … #define QLC_83XX_SRIOV_MODE … #define QLCNIC_BRDTYPE_83XX_10G … #define QLC_83XX_FLASH_SPI_STATUS … #define QLC_83XX_FLASH_SPI_CONTROL … #define QLC_83XX_FLASH_STATUS … #define QLC_83XX_FLASH_CONTROL … #define QLC_83XX_FLASH_ADDR … #define QLC_83XX_FLASH_WRDATA … #define QLC_83XX_FLASH_RDDATA … #define QLC_83XX_FLASH_DIRECT_WINDOW … #define QLC_83XX_FLASH_DIRECT_DATA(DATA) … #define QLC_83XX_FLASH_SECTOR_ERASE_CMD … #define QLC_83XX_FLASH_WRITE_CMD … #define QLC_83XX_FLASH_BULK_WRITE_CMD … #define QLC_83XX_FLASH_READ_RETRY_COUNT … #define QLC_83XX_FLASH_STATUS_READY … #define QLC_83XX_FLASH_WRITE_MIN … #define QLC_83XX_FLASH_WRITE_MAX … #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY … #define QLC_83XX_ERASE_MODE … #define QLC_83XX_WRITE_MODE … #define QLC_83XX_BULK_WRITE_MODE … #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG … #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG … #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL … #define QLC_83XX_FLASH_OEM_ERASE_SIG … #define QLC_83XX_FLASH_OEM_WRITE_SIG … #define QLC_83XX_FLASH_OEM_READ_SIG … #define QLC_83XX_FLASH_ADDR_TEMP_VAL … #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL … #define QLC_83XX_FLASH_WRDATA_DEF … #define QLC_83XX_FLASH_READ_CTRL … #define QLC_83XX_FLASH_SPI_CTRL … #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL … #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL … #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL … #define QLC_83XX_FLASH_FIRST_MS_PATTERN … #define QLC_83XX_FLASH_SECOND_MS_PATTERN … #define QLC_83XX_FLASH_LAST_MS_PATTERN … #define QLC_83xx_FLASH_MAX_WAIT_USEC … #define QLC_83XX_FLASH_LOCK_TIMEOUT … enum qlc_83xx_mbx_cmd_type { … }; enum qlc_83xx_mbx_response_states { … }; #define QLC_83XX_MBX_RESPONSE_FAILED … #define QLC_83XX_MBX_RESPONSE_UNKNOWN … /* Additional registers in 83xx */ enum qlc_83xx_ext_regs { … }; /* Initialize/Stop NIC command bit definitions */ #define QLC_REGISTER_LB_IDC … #define QLC_REGISTER_DCB_AEN … #define QLC_83XX_MULTI_TENANCY_INFO … #define QLC_INIT_FW_RESOURCES … /* 83xx funcitons */ int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *); int qlcnic_83xx_setup_intr(struct qlcnic_adapter *); void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, u16 vlan, struct qlcnic_host_tx_ring *ring); int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int); int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); void qlcnic_83xx_napi_del(struct qlcnic_adapter *); void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); int qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); int qlcnic_ind_rd(struct qlcnic_adapter *, u32); int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, struct qlcnic_host_tx_ring *, int); void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *); void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *, struct qlcnic_host_tx_ring *); int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8); int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, struct qlcnic_adapter *, u32); void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, struct qlcnic_info *); int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *, struct ethtool_coalesce *); int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *); int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *); void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *); irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); irqreturn_t qlcnic_83xx_intr(int, void *); irqreturn_t qlcnic_83xx_tmp_intr(int, void *); void qlcnic_83xx_check_vf(struct qlcnic_adapter *, const struct pci_device_id *); int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); void qlcnic_83xx_idc_aen_work(struct work_struct *); void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); int qlcnic_83xx_init(struct qlcnic_adapter *); int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *); int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *); void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *); int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter, struct ethtool_link_ksettings *ecmd); int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter, const struct ethtool_link_ksettings *ecmd); void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, struct ethtool_pauseparam *); int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, struct ethtool_pauseparam *); int qlcnic_83xx_test_link(struct qlcnic_adapter *); void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter); int qlcnic_83xx_reg_test(struct qlcnic_adapter *); int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); int qlcnic_83xx_loopback_test(struct net_device *, u8); int qlcnic_83xx_interrupt_test(struct net_device *); int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state); int qlcnic_83xx_flash_test(struct qlcnic_adapter *); int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *); int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *); void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *); void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *); int qlcnic_83xx_idc_init(struct qlcnic_adapter *); int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *); int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *); int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *); void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *); int qlcnic_83xx_aer_reset(struct qlcnic_adapter *); void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *); u32 qlcnic_83xx_get_saved_state(void *, u32); void qlcnic_83xx_set_saved_state(void *, u32, u32); void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *); u32 qlcnic_83xx_get_cap_size(void *, int); void qlcnic_83xx_set_sys_info(void *, int, u32); void qlcnic_83xx_store_cap_mask(void *, u32); int qlcnic_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); #endif
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