// SPDX-License-Identifier: GPL-2.0 /* * PCI detection and setup code */ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/msi.h> #include <linux/of_pci.h> #include <linux/pci_hotplug.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/cpumask.h> #include <linux/aer.h> #include <linux/acpi.h> #include <linux/hypervisor.h> #include <linux/irqdomain.h> #include <linux/pm_runtime.h> #include <linux/bitfield.h> #include "pci.h" #define CARDBUS_LATENCY_TIMER … #define CARDBUS_RESERVE_BUSNR … static struct resource busn_resource = …; /* Ugh. Need to stop exporting this to modules. */ LIST_HEAD(…); EXPORT_SYMBOL(…); static LIST_HEAD(pci_domain_busn_res_list); struct pci_domain_busn_res { … }; static struct resource *get_pci_domain_busn_res(int domain_nr) { … } /* * Some device drivers need know if PCI is initiated. * Basically, we think PCI is not initiated when there * is no device to be found on the pci_bus_type. */ int no_pci_devices(void) { … } EXPORT_SYMBOL(…); /* * PCI Bus Class */ static void release_pcibus_dev(struct device *dev) { … } static const struct class pcibus_class = …; static int __init pcibus_class_init(void) { … } postcore_initcall(pcibus_class_init); static u64 pci_size(u64 base, u64 maxbase, u64 mask) { … } static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) { … } #define PCI_COMMAND_DECODE_ENABLE … /** * __pci_read_base - Read a PCI BAR * @dev: the PCI device * @type: type of the BAR * @res: resource buffer to be filled in * @pos: BAR position in the config space * * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. */ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { … } static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { … } static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, bool log) { … } static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, bool log) { … } static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, bool log) { … } static void pci_read_bridge_windows(struct pci_dev *bridge) { … } void pci_read_bridge_bases(struct pci_bus *child) { … } static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) { … } static void pci_release_host_bridge_dev(struct device *dev) { … } static void pci_init_host_bridge(struct pci_host_bridge *bridge) { … } struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) { … } EXPORT_SYMBOL(…); static void devm_pci_alloc_host_bridge_release(void *data) { … } struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, size_t priv) { … } EXPORT_SYMBOL(…); void pci_free_host_bridge(struct pci_host_bridge *bridge) { … } EXPORT_SYMBOL(…); /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ static const unsigned char pcix_bus_speed[] = …; /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ const unsigned char pcie_link_speed[] = …; EXPORT_SYMBOL_GPL(…); const char *pci_speed_string(enum pci_bus_speed speed) { … } EXPORT_SYMBOL_GPL(…); void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) { … } EXPORT_SYMBOL_GPL(…); static unsigned char agp_speeds[] = …; static enum pci_bus_speed agp_speed(int agp3, int agpstat) { … } static void pci_set_bus_speed(struct pci_bus *bus) { … } static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) { … } static void pci_set_bus_msi_domain(struct pci_bus *bus) { … } static bool pci_preserve_config(struct pci_host_bridge *host_bridge) { … } static int pci_register_host_bridge(struct pci_host_bridge *bridge) { … } static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) { … } static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) { … } struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) { … } EXPORT_SYMBOL(…); static void pci_enable_crs(struct pci_dev *pdev) { … } static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, unsigned int available_buses); /** * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus * numbers from EA capability. * @dev: Bridge * @sec: updated with secondary bus number from EA * @sub: updated with subordinate bus number from EA * * If @dev is a bridge with EA capability that specifies valid secondary * and subordinate bus numbers, return true with the bus numbers in @sec * and @sub. Otherwise return false. */ static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) { … } /* * pci_scan_bridge_extend() - Scan buses behind a bridge * @bus: Parent bus the bridge is on * @dev: Bridge itself * @max: Starting subordinate number of buses behind this bridge * @available_buses: Total number of buses available for this bridge and * the devices below. After the minimal bus space has * been allocated the remaining buses will be * distributed equally between hotplug-capable bridges. * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges * that need to be reconfigured. * * If it's a bridge, configure it and scan the bus behind it. * For CardBus bridges, we don't scan behind as the devices will * be handled by the bridge driver itself. * * We need to process bridges in two passes -- first we scan those * already configured by the BIOS and after we are done with all of * them, we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers. * * Return: New subordinate number covering all buses behind this bridge. */ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, int max, unsigned int available_buses, int pass) { … } /* * pci_scan_bridge() - Scan buses behind a bridge * @bus: Parent bus the bridge is on * @dev: Bridge itself * @max: Starting subordinate number of buses behind this bridge * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges * that need to be reconfigured. * * If it's a bridge, configure it and scan the bus behind it. * For CardBus bridges, we don't scan behind as the devices will * be handled by the bridge driver itself. * * We need to process bridges in two passes -- first we scan those * already configured by the BIOS and after we are done with all of * them, we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers. * * Return: New subordinate number covering all buses behind this bridge. */ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) { … } EXPORT_SYMBOL(…); /* * Read interrupt line and base address registers. * The architecture-dependent code can tweak these, of course. */ static void pci_read_irq(struct pci_dev *dev) { … } void set_pcie_port_type(struct pci_dev *pdev) { … } void set_pcie_hotplug_bridge(struct pci_dev *pdev) { … } static void set_pcie_thunderbolt(struct pci_dev *dev) { … } static void set_pcie_untrusted(struct pci_dev *dev) { … } static void pci_set_removable(struct pci_dev *dev) { … } /** * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? * @dev: PCI device * * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that * when forwarding a type1 configuration request the bridge must check that * the extended register address field is zero. The bridge is not permitted * to forward the transactions and must handle it as an Unsupported Request. * Some bridges do not follow this rule and simply drop the extended register * bits, resulting in the standard config space being aliased, every 256 * bytes across the entire configuration space. Test for this condition by * comparing the first dword of each potential alias to the vendor/device ID. * Known offenders: * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) */ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) { … } /** * pci_cfg_space_size_ext - Get the configuration space size of the PCI device * @dev: PCI device * * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices * have 4096 bytes. Even if the device is capable, that doesn't mean we can * access it. Maybe we don't have a way to generate extended config space * accesses, or the device is behind a reverse Express bridge. So we try * reading the dword at 0x100 which must either be 0 or a valid extended * capability header. */ static int pci_cfg_space_size_ext(struct pci_dev *dev) { … } int pci_cfg_space_size(struct pci_dev *dev) { … } static u32 pci_class(struct pci_dev *dev) { … } static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) { … } static u8 pci_hdr_type(struct pci_dev *dev) { … } #define LEGACY_IO_RESOURCE … /** * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability * @dev: PCI device * * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this * at enumeration-time to avoid modifying PCI_COMMAND at run-time. */ static int pci_intx_mask_broken(struct pci_dev *dev) { … } static void early_dump_pci_device(struct pci_dev *pdev) { … } static const char *pci_type_str(struct pci_dev *dev) { … } /** * pci_setup_device - Fill in class and map information of a device * @dev: the device structure to fill * * Initialize the device structure with information about the device's * vendor,class,memory and IO-space addresses, IRQ lines etc. * Called at initialisation of the PCI subsystem and by CardBus services. * Returns 0 on success and negative if unknown type of device (not normal, * bridge or CardBus). */ int pci_setup_device(struct pci_dev *dev) { … } static void pci_configure_mps(struct pci_dev *dev) { … } int pci_configure_extended_tags(struct pci_dev *dev, void *ign) { … } /** * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable * @dev: PCI device to query * * Returns true if the device has enabled relaxed ordering attribute. */ bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { … } EXPORT_SYMBOL(…); static void pci_configure_relaxed_ordering(struct pci_dev *dev) { … } static void pci_configure_eetlp_prefix(struct pci_dev *dev) { … } static void pci_configure_serr(struct pci_dev *dev) { … } static void pci_configure_device(struct pci_dev *dev) { … } static void pci_release_capabilities(struct pci_dev *dev) { … } /** * pci_release_dev - Free a PCI device structure when all users of it are * finished * @dev: device that's been disconnected * * Will be called only by the device core when all users of this PCI device are * done. */ static void pci_release_dev(struct device *dev) { … } static const struct device_type pci_dev_type = …; struct pci_dev *pci_alloc_dev(struct pci_bus *bus) { … } EXPORT_SYMBOL(…); static bool pci_bus_crs_vendor_id(u32 l) { … } static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, int timeout) { … } bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) { … } bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) { … } EXPORT_SYMBOL(…); /* * Read the config data for a PCI device, sanity-check it, * and fill in the dev structure. */ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) { … } void pcie_report_downtraining(struct pci_dev *dev) { … } static void pci_init_capabilities(struct pci_dev *dev) { … } /* * This is the equivalent of pci_host_bridge_msi_domain() that acts on * devices. Firmware interfaces that can select the MSI domain on a * per-device basis should be called from here. */ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) { … } static void pci_set_msi_domain(struct pci_dev *dev) { … } void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) { … } struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) { … } EXPORT_SYMBOL(…); static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) { … } static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) { … } static int only_one_child(struct pci_bus *bus) { … } /** * pci_scan_slot - Scan a PCI slot on a bus for devices * @bus: PCI bus to scan * @devfn: slot number to scan (must have zero function) * * Scan a PCI slot on the specified PCI bus for devices, adding * discovered devices to the @bus->devices list. New devices * will not have is_added set. * * Returns the number of new devices found. */ int pci_scan_slot(struct pci_bus *bus, int devfn) { … } EXPORT_SYMBOL(…); static int pcie_find_smpss(struct pci_dev *dev, void *data) { … } static void pcie_write_mps(struct pci_dev *dev, int mps) { … } static void pcie_write_mrrs(struct pci_dev *dev) { … } static int pcie_bus_configure_set(struct pci_dev *dev, void *data) { … } /* * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, * parents then children fashion. If this changes, then this code will not * work as designed. */ void pcie_bus_configure_settings(struct pci_bus *bus) { … } EXPORT_SYMBOL_GPL(…); /* * Called after each bus is probed, but before its children are examined. This * is marked as __weak because multiple architectures define it. */ void __weak pcibios_fixup_bus(struct pci_bus *bus) { … } /** * pci_scan_child_bus_extend() - Scan devices below a bus * @bus: Bus to scan for devices * @available_buses: Total number of buses available (%0 does not try to * extend beyond the minimal) * * Scans devices below @bus including subordinate buses. Returns new * subordinate number including all the found devices. Passing * @available_buses causes the remaining bus space to be distributed * equally between hotplug-capable bridges to allow future extension of the * hierarchy. */ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, unsigned int available_buses) { … } /** * pci_scan_child_bus() - Scan devices below a bus * @bus: Bus to scan for devices * * Scans devices below @bus including subordinate buses. Returns new * subordinate number including all the found devices. */ unsigned int pci_scan_child_bus(struct pci_bus *bus) { … } EXPORT_SYMBOL_GPL(…); /** * pcibios_root_bridge_prepare - Platform-specific host bridge setup * @bridge: Host bridge to set up * * Default empty implementation. Replace with an architecture-specific setup * routine, if necessary. */ int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) { … } void __weak pcibios_add_bus(struct pci_bus *bus) { … } void __weak pcibios_remove_bus(struct pci_bus *bus) { … } struct pci_bus *pci_create_root_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct list_head *resources) { … } EXPORT_SYMBOL_GPL(…); int pci_host_probe(struct pci_host_bridge *bridge) { … } EXPORT_SYMBOL_GPL(…); int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) { … } int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) { … } void pci_bus_release_busn_res(struct pci_bus *b) { … } int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) { … } EXPORT_SYMBOL(…); struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct list_head *resources) { … } EXPORT_SYMBOL(…); struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata) { … } EXPORT_SYMBOL(…); /** * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices * @bridge: PCI bridge for the bus to scan * * Scan a PCI bus and child buses for new devices, add them, * and enable them, resizing bridge mmio/io resource if necessary * and possible. The caller must ensure the child devices are already * removed for resizing to occur. * * Returns the max number of subordinate bus discovered. */ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) { … } /** * pci_rescan_bus - Scan a PCI bus for devices * @bus: PCI bus to scan * * Scan a PCI bus and child buses for new devices, add them, * and enable them. * * Returns the max number of subordinate bus discovered. */ unsigned int pci_rescan_bus(struct pci_bus *bus) { … } EXPORT_SYMBOL_GPL(…); /* * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal * routines should always be executed under this mutex. */ static DEFINE_MUTEX(pci_rescan_remove_lock); void pci_lock_rescan_remove(void) { … } EXPORT_SYMBOL_GPL(…); void pci_unlock_rescan_remove(void) { … } EXPORT_SYMBOL_GPL(…); static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) { … } void __init pci_sort_breadthfirst(void) { … } int pci_hp_add_bridge(struct pci_dev *dev) { … } EXPORT_SYMBOL_GPL(…);
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