linux/drivers/net/ethernet/qlogic/qed/qed_mfw_hsi.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qed NIC Driver
 * Copyright (c) 2019-2021 Marvell International Ltd.
 */

#ifndef _QED_MFW_HSI_H
#define _QED_MFW_HSI_H

#define MFW_TRACE_SIGNATURE

/* The trace in the buffer */
#define MFW_TRACE_EVENTID_MASK
#define MFW_TRACE_PRM_SIZE_MASK
#define MFW_TRACE_PRM_SIZE_OFFSET
#define MFW_TRACE_ENTRY_SIZE

struct mcp_trace {};

#define VF_MAX_STATIC
#define VF_BITMAP_SIZE_IN_DWORDS
#define VF_BITMAP_SIZE_IN_BYTES

#define EXT_VF_MAX_STATIC
#define EXT_VF_BITMAP_SIZE_IN_DWORDS
#define EXT_VF_BITMAP_SIZE_IN_BYTES
#define ADDED_VF_BITMAP_SIZE

#define MCP_GLOB_PATH_MAX
#define MCP_PORT_MAX
#define MCP_GLOB_PORT_MAX
#define MCP_GLOB_FUNC_MAX

offsize_t;		/* In DWORDS !!! */
/* Offset from the beginning of the MCP scratchpad */
#define OFFSIZE_OFFSET_SHIFT
#define OFFSIZE_OFFSET_MASK
/* Size of specific element (not the whole array if any) */
#define OFFSIZE_SIZE_SHIFT
#define OFFSIZE_SIZE_MASK

#define SECTION_OFFSET(_offsize)

#define QED_SECTION_SIZE(_offsize)

#define SECTION_ADDR(_offsize, idx)

#define SECTION_OFFSIZE_ADDR(_pub_base, _section)

/* PHY configuration */
struct eth_phy_cfg {};

struct port_mf_cfg {};

struct eth_stats {};

struct pkt_type_cnt {};

struct brb_stats {};

struct port_stats {};

struct couple_mode_teaming {};

#define LLDP_CHASSIS_ID_STAT_LEN
#define LLDP_PORT_ID_STAT_LEN
#define DCBX_MAX_APP_PROTOCOL
#define MAX_SYSTEM_LLDP_TLV_DATA
#define MAX_TLV_BUFFER

enum _lldp_agent {};

struct lldp_config_params_s {};

struct lldp_status_params_s {};

struct dcbx_ets_feature {};

#define DCBX_TCP_OOO_TC
#define DCBX_TCP_OOO_K2_4PORT_TC

struct dcbx_app_priority_entry {};

struct dcbx_app_priority_feature {};

struct dcbx_features {};

struct dcbx_local_params {};

struct dcbx_mib {};

struct lldp_system_tlvs_buffer_s {};

struct lldp_received_tlvs_s {};

struct dcb_dscp_map {};

struct mcp_val64 {};

struct generic_idc_msg_s {};

struct pcie_stats_stc {};

enum _attribute_commands_e {};

struct public_global {};

struct fw_flr_mb {};

struct public_path {};

#define FC_NPIV_WWPN_SIZE
#define FC_NPIV_WWNN_SIZE
struct dci_npiv_settings {};

struct dci_fc_npiv_cfg {};

#define MAX_NUMBER_NPIV
struct dci_fc_npiv_tbl {};

struct pause_flood_monitor {};

struct public_port {};

#define MCP_DRV_VER_STR_SIZE
#define MCP_DRV_VER_STR_SIZE_DWORD
#define MCP_DRV_NVM_BUF_LEN
struct drv_version_stc {};

struct public_func {};

struct mcp_mac {};

struct mcp_file_att {};

struct bist_nvm_image_att {};

struct lan_stats_stc {};

struct fcoe_stats_stc {};

struct iscsi_stats_stc {};

struct rdma_stats_stc {};

struct ocbb_data_stc {};

struct fcoe_cap_stc {};

#define MAX_NUM_OF_SENSORS
struct temperature_status_stc {};

/* crash dump configuration header */
struct mdump_config_stc {};

enum resource_id_enum {};

/* Resource ID is to be filled by the driver in the MB request
 * Size, offset & flags to be filled by the MFW in the MB response
 */
struct resource_info {};

struct mcp_wwn {};

#define DRV_ROLE_NONE
#define DRV_ROLE_PREBOOT
#define DRV_ROLE_OS
#define DRV_ROLE_KDUMP

struct load_req_stc {};

struct load_rsp_stc {};

struct mdump_retain_data_stc {};

struct attribute_cmd_write_stc {};

struct lldp_stats_stc {};

struct get_att_ctrl_stc {};

struct trace_filter_stc {};

drv_union_data;

struct public_drv_mb {};

#define DRV_MSG_CODE(_code_)
enum drv_msg_code_enum {};

#define DRV_MSG_CODE_VMAC_TYPE_SHIFT
#define DRV_MSG_CODE_VMAC_TYPE_MASK
#define DRV_MSG_CODE_VMAC_TYPE_MAC
#define DRV_MSG_CODE_VMAC_TYPE_WWNN
#define DRV_MSG_CODE_VMAC_TYPE_WWPN

/* DRV_MSG_CODE_RETAIN_VMAC parameters */
#define DRV_MSG_CODE_RETAIN_VMAC_FUNC_SHIFT
#define DRV_MSG_CODE_RETAIN_VMAC_FUNC_MASK

#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_SHIFT
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_MASK
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_L2
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_ISCSI
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_FCOE
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWNN
#define DRV_MSG_CODE_RETAIN_VMAC_TYPE_WWPN

#define DRV_MSG_CODE_MCP_RESET_FORCE

#define DRV_MSG_CODE_STATS_TYPE_LAN
#define DRV_MSG_CODE_STATS_TYPE_FCOE
#define DRV_MSG_CODE_STATS_TYPE_ISCSI
#define DRV_MSG_CODE_STATS_TYPE_RDMA

#define BW_MAX_MASK
#define BW_MAX_OFFSET
#define BW_MIN_MASK
#define BW_MIN_OFFSET

#define DRV_MSG_FAN_FAILURE_TYPE
#define DRV_MSG_TEMPERATURE_FAILURE_TYPE

#define RESOURCE_CMD_REQ_RESC_MASK
#define RESOURCE_CMD_REQ_RESC_SHIFT
#define RESOURCE_CMD_REQ_OPCODE_MASK
#define RESOURCE_CMD_REQ_OPCODE_SHIFT
#define RESOURCE_OPCODE_REQ
#define RESOURCE_OPCODE_REQ_WO_AGING
#define RESOURCE_OPCODE_REQ_W_AGING
#define RESOURCE_OPCODE_RELEASE
#define RESOURCE_OPCODE_FORCE_RELEASE
#define RESOURCE_CMD_REQ_AGE_MASK
#define RESOURCE_CMD_REQ_AGE_SHIFT

#define RESOURCE_CMD_RSP_OWNER_MASK
#define RESOURCE_CMD_RSP_OWNER_SHIFT
#define RESOURCE_CMD_RSP_OPCODE_MASK
#define RESOURCE_CMD_RSP_OPCODE_SHIFT
#define RESOURCE_OPCODE_GNT
#define RESOURCE_OPCODE_BUSY
#define RESOURCE_OPCODE_RELEASED
#define RESOURCE_OPCODE_RELEASED_PREVIOUS
#define RESOURCE_OPCODE_WRONG_OWNER
#define RESOURCE_OPCODE_UNKNOWN_CMD

#define RESOURCE_DUMP

/* DRV_MSG_CODE_MDUMP_CMD parameters */
#define MDUMP_DRV_PARAM_OPCODE_MASK
#define DRV_MSG_CODE_MDUMP_ACK
#define DRV_MSG_CODE_MDUMP_SET_VALUES
#define DRV_MSG_CODE_MDUMP_TRIGGER
#define DRV_MSG_CODE_MDUMP_GET_CONFIG
#define DRV_MSG_CODE_MDUMP_SET_ENABLE
#define DRV_MSG_CODE_MDUMP_CLEAR_LOGS
#define DRV_MSG_CODE_MDUMP_GET_RETAIN
#define DRV_MSG_CODE_MDUMP_CLR_RETAIN

#define DRV_MSG_CODE_HW_DUMP_TRIGGER

#define DRV_MSG_CODE_MDUMP_FREE_DRIVER_BUF
#define DRV_MSG_CODE_MDUMP_GEN_LINK_DUMP
#define DRV_MSG_CODE_MDUMP_GEN_IDLE_CHK

/* DRV_MSG_CODE_MDUMP_CMD options */
#define MDUMP_DRV_PARAM_OPTION_MASK
#define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_OFFSET
#define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_MASK

/* DRV_MSG_CODE_EXT_PHY_READ/DRV_MSG_CODE_EXT_PHY_WRITE parameters */
#define DRV_MB_PARAM_ADDR_SHIFT
#define DRV_MB_PARAM_ADDR_MASK
#define DRV_MB_PARAM_DEVAD_SHIFT
#define DRV_MB_PARAM_DEVAD_MASK
#define DRV_MB_PARAM_PORT_SHIFT
#define DRV_MB_PARAM_PORT_MASK

/* DRV_MSG_CODE_PMBUS_READ/DRV_MSG_CODE_PMBUS_WRITE parameters */
#define DRV_MB_PARAM_PMBUS_CMD_SHIFT
#define DRV_MB_PARAM_PMBUS_CMD_MASK
#define DRV_MB_PARAM_PMBUS_LEN_SHIFT
#define DRV_MB_PARAM_PMBUS_LEN_MASK
#define DRV_MB_PARAM_PMBUS_DATA_SHIFT
#define DRV_MB_PARAM_PMBUS_DATA_MASK

/* UNLOAD_REQ params */
#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN
#define DRV_MB_PARAM_UNLOAD_WOL_MCP
#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED
#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED

/* UNLOAD_DONE_params */
#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER

/* INIT_PHY params */
#define DRV_MB_PARAM_INIT_PHY_FORCE
#define DRV_MB_PARAM_INIT_PHY_DONT_CARE

/* LLDP / DCBX params*/
#define DRV_MB_PARAM_LLDP_SEND_MASK
#define DRV_MB_PARAM_LLDP_SEND_SHIFT
#define DRV_MB_PARAM_LLDP_AGENT_MASK
#define DRV_MB_PARAM_LLDP_AGENT_SHIFT
#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK
#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_SHIFT
#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK
#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_SHIFT
#define DRV_MB_PARAM_DCBX_NOTIFY_MASK
#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT
#define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_MASK
#define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_SHIFT

#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK
#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT

#define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_MASK
#define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_SHIFT
#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW
#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE

#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI
#define DRV_MB_PARAM_NVM_OFFSET_OFFSET
#define DRV_MB_PARAM_NVM_OFFSET_MASK
#define DRV_MB_PARAM_NVM_LEN_OFFSET
#define DRV_MB_PARAM_NVM_LEN_MASK

#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT
#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK
#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT
#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK

#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT
#define DRV_MB_PARAM_OV_CURR_CFG_MASK
#define DRV_MB_PARAM_OV_CURR_CFG_NONE
#define DRV_MB_PARAM_OV_CURR_CFG_OS
#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC
#define DRV_MB_PARAM_OV_CURR_CFG_OTHER

#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT
#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK
#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK
#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK
#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK
#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK

#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED
#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE

#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT
#define DRV_MB_PARAM_OV_MTU_SIZE_MASK

#define DRV_MB_PARAM_WOL_MASK
#define DRV_MB_PARAM_WOL_DEFAULT
#define DRV_MB_PARAM_WOL_DISABLED
#define DRV_MB_PARAM_WOL_ENABLED

#define DRV_MB_PARAM_ESWITCH_MODE_MASK
#define DRV_MB_PARAM_ESWITCH_MODE_NONE
#define DRV_MB_PARAM_ESWITCH_MODE_VEB
#define DRV_MB_PARAM_ESWITCH_MODE_VEPA

#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK
#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET

#define DRV_MB_PARAM_SET_LED_MODE_OPER
#define DRV_MB_PARAM_SET_LED_MODE_ON
#define DRV_MB_PARAM_SET_LED_MODE_OFF

#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET
#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK
#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET
#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK
#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET
#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK
#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET
#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK

	/* Resource Allocation params - Driver version support */
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT

#define DRV_MB_PARAM_BIST_UNKNOWN_TEST
#define DRV_MB_PARAM_BIST_REGISTER_TEST
#define DRV_MB_PARAM_BIST_CLOCK_TEST
#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES
#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX

#define DRV_MB_PARAM_BIST_RC_UNKNOWN
#define DRV_MB_PARAM_BIST_RC_PASSED
#define DRV_MB_PARAM_BIST_RC_FAILED
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER

#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT
#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK
#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT
#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL
#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL
#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK

/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET
#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK

/* Driver attributes params */
#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET
#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK
#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET
#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK

#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET
#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_IGNORE
#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_MASK
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT
#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK

/*DRV_MSG_CODE_GET_PERM_MAC parametres*/
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_SHIFT
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MASK
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_PF
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_BMC
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_VF
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_LLDP
#define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MAX
#define DRV_MSG_CODE_GET_PERM_MAC_INDEX_SHIFT
#define DRV_MSG_CODE_GET_PERM_MAC_INDEX_MASK

#define FW_MSG_CODE(_code_)
enum fw_msg_code_enum {};

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT

/* Get PF RDMA protocol command response */
#define FW_MB_PARAM_GET_PF_RDMA_NONE
#define FW_MB_PARAM_GET_PF_RDMA_ROCE
#define FW_MB_PARAM_GET_PF_RDMA_IWARP
#define FW_MB_PARAM_GET_PF_RDMA_BOTH

/* Get MFW feature support response */
#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ
#define FW_MB_PARAM_FEATURE_SUPPORT_EEE
#define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO
#define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET
#define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD
#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL
#define FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL
#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP
#define FW_MB_PARAM_FEATURE_SUPPORT_VF_DPM
#define FW_MB_PARAM_FEATURE_SUPPORT_IDLE_CHK
#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK
#define FW_MB_PARAM_FEATURE_SUPPORT_DISABLE_LLDP
#define FW_MB_PARAM_FEATURE_SUPPORT_ENHANCED_SYS_LCK
#define FW_MB_PARAM_FEATURE_SUPPORT_RESTORE_DEFAULT_CFG

#define FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED

#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR

#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT

#define FW_MB_PARAM_PPFID_BITMAP_MASK
#define FW_MB_PARAM_PPFID_BITMAP_SHIFT

#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK
#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT
#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK
#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT

enum MFW_DRV_MSG_TYPE {};

#define MFW_DRV_MSG_MAX_DWORDS(msgs)
#define MFW_DRV_MSG_DWORD(msg_id)
#define MFW_DRV_MSG_OFFSET(msg_id)
#define MFW_DRV_MSG_MASK(msg_id)

struct public_mfw_mb {};

enum public_sections {};

struct drv_ver_info_stc {};

/* Runtime data needs about 1/2K. We use 2K to be on the safe side.
 * Please make sure data does not exceed this size.
 */
#define NUM_RUNTIME_DWORDS
struct drv_init_hw_stc {};

struct mcp_public_data {};

#define I2C_TRANSCEIVER_ADDR
#define MAX_I2C_TRANSACTION_SIZE
#define MAX_I2C_TRANSCEIVER_PAGE_SIZE

/* OCBB definitions */
enum tlvs {};

#define I2C_DEV_ADDR_A2
#define SFP_EEPROM_A2_TEMPERATURE_ADDR
#define SFP_EEPROM_A2_TEMPERATURE_SIZE
#define SFP_EEPROM_A2_VCC_ADDR
#define SFP_EEPROM_A2_VCC_SIZE
#define SFP_EEPROM_A2_TX_BIAS_ADDR
#define SFP_EEPROM_A2_TX_BIAS_SIZE
#define SFP_EEPROM_A2_TX_POWER_ADDR
#define SFP_EEPROM_A2_TX_POWER_SIZE
#define SFP_EEPROM_A2_RX_POWER_ADDR
#define SFP_EEPROM_A2_RX_POWER_SIZE

#define I2C_DEV_ADDR_A0
#define QSFP_EEPROM_A0_TEMPERATURE_ADDR
#define QSFP_EEPROM_A0_TEMPERATURE_SIZE
#define QSFP_EEPROM_A0_VCC_ADDR
#define QSFP_EEPROM_A0_VCC_SIZE
#define QSFP_EEPROM_A0_TX1_BIAS_ADDR
#define QSFP_EEPROM_A0_TX1_BIAS_SIZE
#define QSFP_EEPROM_A0_TX1_POWER_ADDR
#define QSFP_EEPROM_A0_TX1_POWER_SIZE
#define QSFP_EEPROM_A0_RX1_POWER_ADDR
#define QSFP_EEPROM_A0_RX1_POWER_SIZE

struct nvm_cfg_mac_address {};

struct nvm_cfg1_glob {};

struct nvm_cfg1_path {};

struct nvm_cfg1_port {};

struct nvm_cfg1_func {};

struct nvm_cfg1 {};

struct board_info {};

struct trace_module_info {};

#define NUM_TRACE_MODULES

enum nvm_cfg_sections {};

struct nvm_cfg {};

#define PORT_0
#define PORT_1
#define PORT_2
#define PORT_3

extern struct spad_layout g_spad;
struct spad_layout {};

#define MCP_SPAD_SIZE

#define SPAD_OFFSET(addr)

#define TO_OFFSIZE(_offset, _size)

enum spad_sections {};

#define STRUCT_OFFSET(f)

/* This section is located at a fixed location in the beginning of the
 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
 * All the rest of data has a floating location which differs from version to
 * version, and is pointed by the mcp_meta_data below.
 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
 * with it from nvram in order to clear this portion.
 */
struct static_init {};

#define CRC_MAGIC_VALUE
#define CRC32_POLYNOMIAL
#define _KB(x)
#define _MB(x)
#define NVM_CRC_SIZE
enum nvm_sw_arbitrator {};

struct legacy_bootstrap_region {};

struct nvm_code_entry {};

enum nvm_image_type {};

#define MAX_NVM_DIR_ENTRIES

struct nvm_dir_meta {};

struct nvm_dir {};

#define NVM_DIR_SIZE(_num_images)

struct nvm_vpd_image {};

#define DIR_ID_1
#define DIR_ID_2
#define MAX_DIR_IDS

#define MFW_BUNDLE_1
#define MFW_BUNDLE_2
#define MAX_MFW_BUNDLES

#define FLASH_PAGE_SIZE
#define NVM_DIR_MAX_SIZE
#define LEGACY_ASIC_MIM_MAX_SIZE

#define FPGA_MIM_MAX_SIZE

#define LIM_MAX_SIZE
#define LIM_OFFSET
#define NVM_RSV_SIZE
#define GET_MIM_MAX_SIZE(is_asic, is_e4)
#define GET_MIM_OFFSET(idx, is_asic, is_e4)
#define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4)

nvm_dir_union;

struct nvm_image {};

#define NVM_OFFSET(f)

struct hw_set_info {};

struct hw_set_image {};

#define MAX_SUPPORTED_NVM_OPTIONS

#define NVM_META_BIN_OPTION_OFFSET_MASK
#define NVM_META_BIN_OPTION_OFFSET_SHIFT
#define NVM_META_BIN_OPTION_LEN_MASK
#define NVM_META_BIN_OPTION_LEN_OFFSET
#define NVM_META_BIN_OPTION_ENTITY_MASK
#define NVM_META_BIN_OPTION_ENTITY_SHIFT
#define NVM_META_BIN_OPTION_ENTITY_GLOB
#define NVM_META_BIN_OPTION_ENTITY_PORT
#define NVM_META_BIN_OPTION_ENTITY_FUNC
#define NVM_META_BIN_OPTION_CONFIG_TYPE_MASK
#define NVM_META_BIN_OPTION_CONFIG_TYPE_SHIFT
#define NVM_META_BIN_OPTION_CONFIG_TYPE_USER
#define NVM_META_BIN_OPTION_CONFIG_TYPE_FIXED
#define NVM_META_BIN_OPTION_CONFIG_TYPE_FORCED

struct nvm_meta_bin_t {};
#endif