// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) /* QLogic qed NIC Driver * Copyright (c) 2015-2017 QLogic Corporation * Copyright (c) 2019-2021 Marvell International Ltd. */ #include <linux/types.h> #include <linux/crc8.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/string.h> #include "qed_hsi.h" #include "qed_hw.h" #include "qed_init_ops.h" #include "qed_iro_hsi.h" #include "qed_reg_addr.h" #define CDU_VALIDATION_DEFAULT_CFG … static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = …; static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = …; /* General constants */ #define QM_PQ_MEM_4KB(pq_size) … #define QM_PQ_SIZE_256B(pq_size) … #define QM_INVALID_PQ_ID … /* Max link speed (in Mbps) */ #define QM_MAX_LINK_SPEED … /* Feature enable */ #define QM_BYPASS_EN … #define QM_BYTE_CRD_EN … /* Initial VOQ byte credit */ #define QM_INITIAL_VOQ_BYTE_CRD … /* Other PQ constants */ #define QM_OTHER_PQS_PER_PF … /* VOQ constants */ #define MAX_NUM_VOQS … #define VOQS_BIT_MASK … /* WFQ constants */ /* PF WFQ increment value, 0x9000 = 4*9*1024 */ #define QM_PF_WFQ_INC_VAL(weight) … /* PF WFQ Upper bound, in MB, 10 * burst size of 1ms in 50Gbps */ #define QM_PF_WFQ_UPPER_BOUND … /* PF WFQ max increment value, 0.7 * upper bound */ #define QM_PF_WFQ_MAX_INC_VAL … /* Number of VOQs in E5 PF WFQ credit register (QmWfqCrd) */ #define QM_PF_WFQ_CRD_E5_NUM_VOQS … /* VP WFQ increment value */ #define QM_VP_WFQ_INC_VAL(weight) … /* VP WFQ min increment value */ #define QM_VP_WFQ_MIN_INC_VAL … /* VP WFQ max increment value, 2^30 */ #define QM_VP_WFQ_MAX_INC_VAL … /* VP WFQ bypass threshold */ #define QM_VP_WFQ_BYPASS_THRESH … /* VP RL credit task cost */ #define QM_VP_RL_CRD_TASK_COST … /* Bit of VOQ in VP WFQ PQ map */ #define QM_VP_WFQ_PQ_VOQ_SHIFT … /* Bit of PF in VP WFQ PQ map */ #define QM_VP_WFQ_PQ_PF_SHIFT … /* RL constants */ /* Period in us */ #define QM_RL_PERIOD … /* Period in 25MHz cycles */ #define QM_RL_PERIOD_CLK_25M … /* RL increment value - rate is specified in mbps */ #define QM_RL_INC_VAL(rate) … /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */ #define QM_PF_RL_UPPER_BOUND … /* Max PF RL increment value is 0.7 * upper bound */ #define QM_PF_RL_MAX_INC_VAL … /* QCN RL Upper bound, speed is in Mpbs */ #define QM_GLOBAL_RL_UPPER_BOUND(speed) … /* AFullOprtnstcCrdMask constants */ #define QM_OPPOR_LINE_VOQ_DEF … #define QM_OPPOR_FW_STOP_DEF … #define QM_OPPOR_PQ_EMPTY_DEF … /* Command Queue constants */ /* Pure LB CmdQ lines (+spare) */ #define PBF_CMDQ_PURE_LB_LINES … #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) … #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) … /* Returns the VOQ line credit for the specified number of PBF command lines. * PBF lines are specified in 256b units. */ #define QM_VOQ_LINE_CRD(pbf_cmd_lines) … /* BTB: blocks constants (block size = 256B) */ /* 256B blocks in 9700B packet */ #define BTB_JUMBO_PKT_BLOCKS … /* Headroom per-port */ #define BTB_HEADROOM_BLOCKS … #define BTB_PURE_LB_FACTOR … /* Factored (hence really 0.7) */ #define BTB_PURE_LB_RATIO … /* QM stop command constants */ #define QM_STOP_PQ_MASK_WIDTH … #define QM_STOP_CMD_ADDR … #define QM_STOP_CMD_STRUCT_SIZE … #define QM_STOP_CMD_PAUSE_MASK_OFFSET … #define QM_STOP_CMD_PAUSE_MASK_SHIFT … #define QM_STOP_CMD_PAUSE_MASK_MASK … #define QM_STOP_CMD_GROUP_ID_OFFSET … #define QM_STOP_CMD_GROUP_ID_SHIFT … #define QM_STOP_CMD_GROUP_ID_MASK … #define QM_STOP_CMD_PQ_TYPE_OFFSET … #define QM_STOP_CMD_PQ_TYPE_SHIFT … #define QM_STOP_CMD_PQ_TYPE_MASK … #define QM_STOP_CMD_MAX_POLL_COUNT … #define QM_STOP_CMD_POLL_PERIOD_US … /* QM command macros */ #define QM_CMD_STRUCT_SIZE(cmd) … #define QM_CMD_SET_FIELD(var, cmd, field, value) … #define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, rl_valid, \ rl_id, ext_voq, wrr) … #define WRITE_PQ_INFO_TO_RAM … #define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) … #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) … static const char * const s_protocol_types[] = …; static const char *s_ramrod_cmd_ids[][28] = …; /******************** INTERNAL IMPLEMENTATION *********************/ /* Returns the external VOQ number */ static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn, u8 port_id, u8 tc, u8 max_phys_tcs_per_port) { … } /* Prepare PF RL enable/disable runtime init values */ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en) { … } /* Prepare PF WFQ enable/disable runtime init values */ static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en) { … } /* Prepare global RL enable/disable runtime init values */ static void qed_enable_global_rl(struct qed_hwfn *p_hwfn, bool global_rl_en) { … } /* Prepare VPORT WFQ enable/disable runtime init values */ static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en) { … } /* Prepare runtime init values to allocate PBF command queue lines for * the specified VOQ. */ static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn, u8 ext_voq, u16 cmdq_lines) { … } /* Prepare runtime init values to allocate PBF command queue lines. */ static void qed_cmdq_lines_rt_init(struct qed_hwfn *p_hwfn, u8 max_ports_per_engine, u8 max_phys_tcs_per_port, struct init_qm_port_params port_params[MAX_NUM_PORTS]) { … } /* Prepare runtime init values to allocate guaranteed BTB blocks for the * specified port. The guaranteed BTB space is divided between the TCs as * follows (shared space Is currently not used): * 1. Parameters: * B - BTB blocks for this port * C - Number of physical TCs for this port * 2. Calculation: * a. 38 blocks (9700B jumbo frame) are allocated for global per port * headroom. * b. B = B - 38 (remainder after global headroom allocation). * c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ. * d. B = B - MAX(38, B/(C+0.7)) (remainder after pure LB allocation). * e. B/C blocks are allocated for each physical TC. * Assumptions: * - MTU is up to 9700 bytes (38 blocks) * - All TCs are considered symmetrical (same rate and packet size) * - No optimization for lossy TC (all are considered lossless). Shared space * is not enabled and allocated for each TC. */ static void qed_btb_blocks_rt_init(struct qed_hwfn *p_hwfn, u8 max_ports_per_engine, u8 max_phys_tcs_per_port, struct init_qm_port_params port_params[MAX_NUM_PORTS]) { … } /* Prepare runtime init values for the specified RL. * Set max link speed (100Gbps) per rate limiter. * Return -1 on error. */ static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn) { … } /* Returns the upper bound for the specified Vport RL parameters. * link_speed is in Mbps. * Returns 0 in case of error. */ static u32 qed_get_vport_rl_upper_bound(enum init_qm_rl_type vport_rl_type, u32 link_speed) { … } /* Prepare VPORT RL runtime init values. * Return -1 on error. */ static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn, u16 start_rl, u16 num_rls, u32 link_speed, struct init_qm_rl_params *rl_params) { … } /* Prepare Tx PQ mapping runtime init values for the specified PF */ static int qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct qed_qm_pf_rt_init_params *p_params, u32 base_mem_addr_4kb) { … } /* Prepare Other PQ mapping runtime init values for the specified PF */ static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, bool is_pf_loading, u32 num_pf_cids, u32 num_tids, u32 base_mem_addr_4kb) { … } /* Prepare PF WFQ runtime init values for the specified PF. * Return -1 on error. */ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn, struct qed_qm_pf_rt_init_params *p_params) { … } /* Prepare PF RL runtime init values for the specified PF. * Return -1 on error. */ static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl) { … } /* Prepare VPORT WFQ runtime init values for the specified VPORTs. * Return -1 on error. */ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn, u16 num_vports, struct init_qm_vport_params *vport_params) { … } static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb) { … } /******************** INTERFACE IMPLEMENTATION *********************/ u32 qed_qm_pf_mem_size(u32 num_pf_cids, u32 num_vf_cids, u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs) { … } int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, struct qed_qm_common_rt_init_params *p_params) { … } int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct qed_qm_pf_rt_init_params *p_params) { … } int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq) { … } int qed_init_pf_rl(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl) { … } int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq) { … } int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 first_tx_pq_id, u16 wfq) { … } int qed_init_global_rl(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit, enum init_qm_rl_type vport_rl_type) { … } bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool is_release_cmd, bool is_tx_pq, u16 start_pq, u16 num_pqs) { … } #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) … #define PRS_ETH_TUNN_OUTPUT_FORMAT … #define PRS_ETH_OUTPUT_FORMAT … #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) … /** * qed_dmae_to_grc() - Internal function for writing from host to * wide-bus registers (split registers are not supported yet). * * @p_hwfn: HW device data. * @p_ptt: PTT window used for writing the registers. * @p_data: Pointer to source data. * @addr: Destination register address. * @len_in_dwords: Data length in dwords (u32). * * Return: Length of the written data in dwords (u32) or -1 on invalid * input. */ static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, __le32 *p_data, u32 addr, u32 len_in_dwords) { … } void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 dest_port) { … } void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool vxlan_enable) { … } void qed_set_gre_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool eth_gre_enable, bool ip_gre_enable) { … } void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 dest_port) { … } void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool eth_geneve_enable, bool ip_geneve_enable) { … } #define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET … #define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT … void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool enable) { … } #define T_ETH_PACKET_ACTION_GFT_EVENTID … #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR … #define T_ETH_PACKET_MATCH_RFS_EVENTID … #define PARSER_ETH_CONN_CM_HDR … #define CAM_LINE_SIZE … #define RAM_LINE_SIZE … #define REG_SIZE … void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id) { … } void qed_gft_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id, bool tcp, bool udp, bool ipv4, bool ipv6, enum gft_profile_type profile_type) { … } DECLARE_CRC8_TABLE(cdu_crc8_table); /* Calculate and return CDU validation byte per connection type/region/cid */ static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid) { … } /* Calcualte and set validation bytes for session context */ void qed_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size, u8 ctx_type, u32 cid) { … } /* Calcualte and set validation bytes for task context */ void qed_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, u8 ctx_type, u32 tid) { … } /* Memset session context to 0 while preserving validation bytes */ void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) { … } /* Memset task context to 0 while preserving validation bytes */ void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) { … } /* Enable and configure context validation */ void qed_enable_context_validation(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } const char *qed_get_protocol_type_str(u32 protocol_type) { … } const char *qed_get_ramrod_cmd_id_str(u32 protocol_type, u32 ramrod_cmd_id) { … } static u32 qed_get_rdma_assert_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id) { … } void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 assert_level[NUM_STORMS]) { … } #define PHYS_ADDR_DWORDS … #define OVERLAY_HDR_SIZE_DWORDS … static u32 qed_get_overlay_addr_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id) { … } struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn, const u32 * const fw_overlay_in_buf, u32 buf_size_in_bytes) { … } void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct phys_mem_desc *fw_overlay_mem) { … } void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn, struct phys_mem_desc **fw_overlay_mem) { … }
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