// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) /* QLogic qed NIC Driver * Copyright (c) 2015-2017 QLogic Corporation * Copyright (c) 2019-2020 Marvell International Ltd. */ #include <linux/stddef.h> #include <linux/pci.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/delay.h> #include <asm/byteorder.h> #include <linux/dma-mapping.h> #include <linux/string.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/workqueue.h> #include <linux/ethtool.h> #include <linux/etherdevice.h> #include <linux/vmalloc.h> #include <linux/crash_dump.h> #include <linux/crc32.h> #include <linux/qed/qed_if.h> #include <linux/qed/qed_ll2_if.h> #include <net/devlink.h> #include <linux/phylink.h> #include "qed.h" #include "qed_sriov.h" #include "qed_sp.h" #include "qed_dev_api.h" #include "qed_ll2.h" #include "qed_fcoe.h" #include "qed_iscsi.h" #include "qed_mcp.h" #include "qed_reg_addr.h" #include "qed_hw.h" #include "qed_selftest.h" #include "qed_debug.h" #include "qed_devlink.h" #define QED_ROCE_QPS … #define QED_ROCE_DPIS … #define QED_RDMA_SRQS … #define QED_NVM_CFG_GET_FLAGS … #define QED_NVM_CFG_GET_PF_FLAGS … #define QED_NVM_CFG_MAX_ATTRS … static char version[] = …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; #define FW_FILE_VERSION … #define QED_FW_FILE_NAME … MODULE_FIRMWARE(…); /* MFW speed capabilities maps */ struct qed_mfw_speed_map { … }; #define QED_MFW_SPEED_MAP(type, arr) … static const u32 qed_mfw_ext_1g[] __initconst = …; static const u32 qed_mfw_ext_10g[] __initconst = …; static const u32 qed_mfw_ext_25g[] __initconst = …; static const u32 qed_mfw_ext_40g[] __initconst = …; static const u32 qed_mfw_ext_50g_base_r[] __initconst = …; static const u32 qed_mfw_ext_50g_base_r2[] __initconst = …; static const u32 qed_mfw_ext_100g_base_r2[] __initconst = …; static const u32 qed_mfw_ext_100g_base_r4[] __initconst = …; static struct qed_mfw_speed_map qed_mfw_ext_maps[] __ro_after_init = …; static const u32 qed_mfw_legacy_1g[] __initconst = …; static const u32 qed_mfw_legacy_10g[] __initconst = …; static const u32 qed_mfw_legacy_20g[] __initconst = …; static const u32 qed_mfw_legacy_25g[] __initconst = …; static const u32 qed_mfw_legacy_40g[] __initconst = …; static const u32 qed_mfw_legacy_50g[] __initconst = …; static const u32 qed_mfw_legacy_bb_100g[] __initconst = …; static struct qed_mfw_speed_map qed_mfw_legacy_maps[] __ro_after_init = …; static void __init qed_mfw_speed_map_populate(struct qed_mfw_speed_map *map) { … } static void __init qed_mfw_speed_maps_init(void) { … } static int __init qed_init(void) { … } module_init(…) …; static void __exit qed_exit(void) { … } module_exit(qed_exit); static void qed_free_pci(struct qed_dev *cdev) { … } #define PCI_REVISION_ID_ERROR_VAL … /* Performs PCI initializations as well as initializing PCI-related parameters * in the device structrue. Returns 0 in case of success. */ static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev) { … } int qed_fill_dev_info(struct qed_dev *cdev, struct qed_dev_info *dev_info) { … } static void qed_free_cdev(struct qed_dev *cdev) { … } static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev) { … } /* Sets the requested power state */ static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state) { … } /* probing */ static struct qed_dev *qed_probe(struct pci_dev *pdev, struct qed_probe_params *params) { … } static void qed_remove(struct qed_dev *cdev) { … } static void qed_disable_msix(struct qed_dev *cdev) { … } static int qed_enable_msix(struct qed_dev *cdev, struct qed_int_params *int_params) { … } /* This function outputs the int mode and the number of enabled msix vector */ static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode) { … } static void qed_simd_handler_config(struct qed_dev *cdev, void *token, int index, void(*handler)(void *)) { … } static void qed_simd_handler_clean(struct qed_dev *cdev, int index) { … } static irqreturn_t qed_msix_sp_int(int irq, void *tasklet) { … } static irqreturn_t qed_single_int(int irq, void *dev_instance) { … } int qed_slowpath_irq_req(struct qed_hwfn *hwfn) { … } static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn) { … } void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn) { … } static void qed_slowpath_irq_free(struct qed_dev *cdev) { … } static int qed_nic_stop(struct qed_dev *cdev) { … } static int qed_nic_setup(struct qed_dev *cdev) { … } static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt) { … } static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) { … } static int qed_slowpath_setup_int(struct qed_dev *cdev, enum qed_int_mode int_mode) { … } static int qed_slowpath_vf_setup_int(struct qed_dev *cdev) { … } u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len, u8 *input_buf, u32 max_size, u8 *unzip_buf) { … } static int qed_alloc_stream_mem(struct qed_dev *cdev) { … } static void qed_free_stream_mem(struct qed_dev *cdev) { … } static void qed_update_pf_params(struct qed_dev *cdev, struct qed_pf_params *params) { … } #define QED_PERIODIC_DB_REC_COUNT … #define QED_PERIODIC_DB_REC_INTERVAL_MS … #define QED_PERIODIC_DB_REC_INTERVAL … static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn, enum qed_slowpath_wq_flag wq_flag, unsigned long delay) { … } void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn) { … } static void qed_slowpath_wq_stop(struct qed_dev *cdev) { … } static void qed_slowpath_task(struct work_struct *work) { … } static int qed_slowpath_wq_start(struct qed_dev *cdev) { … } static int qed_slowpath_start(struct qed_dev *cdev, struct qed_slowpath_params *params) { … } static int qed_slowpath_stop(struct qed_dev *cdev) { … } static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE]) { … } static u32 qed_sb_init(struct qed_dev *cdev, struct qed_sb_info *sb_info, void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id, enum qed_sb_type type) { … } static u32 qed_sb_release(struct qed_dev *cdev, struct qed_sb_info *sb_info, u16 sb_id, enum qed_sb_type type) { … } static bool qed_can_link_change(struct qed_dev *cdev) { … } static void qed_set_ext_speed_params(struct qed_mcp_link_params *link_params, const struct qed_link_params *params) { … } static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) { … } static int qed_get_port_type(u32 media_type) { … } static int qed_get_link_data(struct qed_hwfn *hwfn, struct qed_mcp_link_params *params, struct qed_mcp_link_state *link, struct qed_mcp_link_capabilities *link_caps) { … } static void qed_fill_link_capability(struct qed_hwfn *hwfn, struct qed_ptt *ptt, u32 capability, unsigned long *if_caps) { … } static void qed_lp_caps_to_speed_mask(u32 caps, u32 *speed_mask) { … } static void qed_fill_link(struct qed_hwfn *hwfn, struct qed_ptt *ptt, struct qed_link_output *if_link) { … } static void qed_get_current_link(struct qed_dev *cdev, struct qed_link_output *if_link) { … } void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt) { … } void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt) { … } static int qed_drain(struct qed_dev *cdev) { … } static u32 qed_nvm_flash_image_access_crc(struct qed_dev *cdev, struct qed_nvm_image_att *nvm_image, u32 *crc) { … } /* Binary file format - * /----------------------------------------------------------------------\ * 0B | 0x4 [command index] | * 4B | image_type | Options | Number of register settings | * 8B | Value | * 12B | Mask | * 16B | Offset | * \----------------------------------------------------------------------/ * There can be several Value-Mask-Offset sets as specified by 'Number of...'. * Options - 0'b - Calculate & Update CRC for image */ static int qed_nvm_flash_image_access(struct qed_dev *cdev, const u8 **data, bool *check_resp) { … } /* Binary file format - * /----------------------------------------------------------------------\ * 0B | 0x3 [command index] | * 4B | b'0: check_response? | b'1-31 reserved | * 8B | File-type | reserved | * 12B | Image length in bytes | * \----------------------------------------------------------------------/ * Start a new file of the provided type */ static int qed_nvm_flash_image_file_start(struct qed_dev *cdev, const u8 **data, bool *check_resp) { … } /* Binary file format - * /----------------------------------------------------------------------\ * 0B | 0x2 [command index] | * 4B | Length in bytes | * 8B | b'0: check_response? | b'1-31 reserved | * 12B | Offset in bytes | * 16B | Data ... | * \----------------------------------------------------------------------/ * Write data as part of a file that was previously started. Data should be * of length equal to that provided in the message */ static int qed_nvm_flash_image_file_data(struct qed_dev *cdev, const u8 **data, bool *check_resp) { … } /* Binary file format [General header] - * /----------------------------------------------------------------------\ * 0B | QED_NVM_SIGNATURE | * 4B | Length in bytes | * 8B | Highest command in this batchfile | Reserved | * \----------------------------------------------------------------------/ */ static int qed_nvm_flash_image_validate(struct qed_dev *cdev, const struct firmware *image, const u8 **data) { … } /* Binary file format - * /----------------------------------------------------------------------\ * 0B | 0x5 [command index] | * 4B | Number of config attributes | Reserved | * 4B | Config ID | Entity ID | Length | * 4B | Value | * | | * \----------------------------------------------------------------------/ * There can be several cfg_id-entity_id-Length-Value sets as specified by * 'Number of config attributes'. * * The API parses config attributes from the user provided buffer and flashes * them to the respective NVM path using Management FW inerface. */ static int qed_nvm_flash_cfg_write(struct qed_dev *cdev, const u8 **data) { … } #define QED_MAX_NVM_BUF_LEN … static int qed_nvm_flash_cfg_len(struct qed_dev *cdev, u32 cmd) { … } static int qed_nvm_flash_cfg_read(struct qed_dev *cdev, u8 **data, u32 cmd, u32 entity_id) { … } static int qed_nvm_flash(struct qed_dev *cdev, const char *name) { … } static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type, u8 *buf, u16 len) { … } void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn) { … } static const char * const qed_hw_err_type_descr[] = …; void qed_hw_error_occurred(struct qed_hwfn *p_hwfn, enum qed_hw_err_type err_type) { … } static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal, void *handle) { … } static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) { … } int qed_recovery_process(struct qed_dev *cdev) { … } static int qed_update_wol(struct qed_dev *cdev, bool enabled) { … } static int qed_update_drv_state(struct qed_dev *cdev, bool active) { … } static int qed_update_mac(struct qed_dev *cdev, const u8 *mac) { … } static int qed_update_mtu(struct qed_dev *cdev, u16 mtu) { … } static int qed_get_sb_info(struct qed_dev *cdev, struct qed_sb_info *sb, u16 qid, struct qed_sb_info_dbg *sb_dbg) { … } static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf, u8 dev_addr, u32 offset, u32 len) { … } static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val) { … } static __printf(2, 3) void qed_mfw_report(struct qed_dev *cdev, char *fmt, ...) { … } static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev) { … } static int qed_get_esl_status(struct qed_dev *cdev, bool *esl_active) { … } static struct qed_selftest_ops qed_selftest_ops_pass = …; const struct qed_common_ops qed_common_ops_pass = …; void qed_get_protocol_stats(struct qed_dev *cdev, enum qed_mcp_protocol_type type, union qed_mcp_protocol_stats *stats) { … } int qed_mfw_tlv_req(struct qed_hwfn *hwfn) { … } static void qed_fill_generic_tlv_data(struct qed_dev *cdev, struct qed_mfw_tlv_generic *tlv) { … } int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type, union qed_mfw_tlv_data *tlv_buf) { … } unsigned long qed_get_epoch_time(void) { … }
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