// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) /* QLogic qed NIC Driver * Copyright (c) 2015-2017 QLogic Corporation * Copyright (c) 2019-2020 Marvell International Ltd. */ #include <linux/types.h> #include <asm/byteorder.h> #include <linux/io.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/string.h> #include "qed.h" #include "qed_hsi.h" #include "qed_hw.h" #include "qed_init_ops.h" #include "qed_int.h" #include "qed_mcp.h" #include "qed_reg_addr.h" #include "qed_sp.h" #include "qed_sriov.h" #include "qed_vf.h" struct qed_pi_info { … }; struct qed_sb_sp_info { … }; enum qed_attention_type { … }; #define SB_ATTN_ALIGNED_SIZE(p_hwfn) … struct aeu_invert_reg_bit { … }; struct aeu_invert_reg { … }; #define MAX_ATTN_GRPS … #define NUM_ATTN_REGS … /* Specific HW attention callbacks */ static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) { … } #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS … #define ATTENTION_INCORRECT_ACCESS_WR_MASK … #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT … #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK … #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT … #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK … #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT … #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK … #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT … #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK … #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT … #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK … #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT … static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) { … } #define QED_GRC_ATTENTION_VALID_BIT … #define QED_GRC_ATTENTION_ADDRESS_MASK … #define QED_GRC_ATTENTION_ADDRESS_SHIFT … #define QED_GRC_ATTENTION_RDWR_BIT … #define QED_GRC_ATTENTION_MASTER_MASK … #define QED_GRC_ATTENTION_MASTER_SHIFT … #define QED_GRC_ATTENTION_PF_MASK … #define QED_GRC_ATTENTION_PF_SHIFT … #define QED_GRC_ATTENTION_VF_MASK … #define QED_GRC_ATTENTION_VF_SHIFT … #define QED_GRC_ATTENTION_PRIV_MASK … #define QED_GRC_ATTENTION_PRIV_SHIFT … #define QED_GRC_ATTENTION_PRIV_VF … static const char *attn_master_to_str(u8 master) { … } static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) { … } #define PGLUE_ATTENTION_VALID … #define PGLUE_ATTENTION_RD_VALID … #define PGLUE_ATTENTION_DETAILS_PFID_MASK … #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT … #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK … #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT … #define PGLUE_ATTENTION_DETAILS_VFID_MASK … #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT … #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK … #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT … #define PGLUE_ATTENTION_DETAILS2_BME_MASK … #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT … #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK … #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT … #define PGLUE_ATTENTION_ICPL_VALID … #define PGLUE_ATTENTION_ZLR_VALID … #define PGLUE_ATTENTION_ILT_VALID … int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool hw_init) { … } static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) { … } static int qed_fw_assertion(struct qed_hwfn *p_hwfn) { … } static int qed_general_attention_35(struct qed_hwfn *p_hwfn) { … } #define QED_DORQ_ATTENTION_REASON_MASK … #define QED_DORQ_ATTENTION_OPAQUE_MASK … #define QED_DORQ_ATTENTION_OPAQUE_SHIFT … #define QED_DORQ_ATTENTION_SIZE_MASK … #define QED_DORQ_ATTENTION_SIZE_SHIFT … #define QED_DB_REC_COUNT … #define QED_DB_REC_INTERVAL … static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) { … } static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) { … } static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) { … } static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) { … } /* Instead of major changes to the data-structure, we have a some 'special' * identifiers for sources that changed meaning between adapters. */ enum aeu_invert_reg_special_type { … }; static struct aeu_invert_reg_bit aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = …; /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = …; static struct aeu_invert_reg_bit * qed_int_aeu_translate(struct qed_hwfn *p_hwfn, struct aeu_invert_reg_bit *p_bit) { … } static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, struct aeu_invert_reg_bit *p_bit) { … } #define ATTN_STATE_BITS … #define ATTN_BITS_MASKABLE … struct qed_sb_attn_info { … }; static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, struct qed_sb_attn_info *p_sb_desc) { … } /** * qed_int_assertion() - Handle asserted attention bits. * * @p_hwfn: HW device data. * @asserted_bits: Newly asserted bits. * * Return: Zero value. */ static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) { … } static void qed_int_attn_print(struct qed_hwfn *p_hwfn, enum block_id id, enum dbg_attn_type type, bool b_clear) { … } /** * qed_int_deassertion_aeu_bit() - Handles the effects of a single * cause of the attention. * * @p_hwfn: HW device data. * @p_aeu: Descriptor of an AEU bit which caused the attention. * @aeu_en_reg: Register offset of the AEU enable reg. which configured * this bit to this group. * @p_bit_name: AEU bit description for logging purposes. * @bitmask: Index of this bit in the aeu_en_reg. * * Return: Zero on success, negative errno otherwise. */ static int qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, struct aeu_invert_reg_bit *p_aeu, u32 aeu_en_reg, const char *p_bit_name, u32 bitmask) { … } /** * qed_int_deassertion_parity() - Handle a single parity AEU source. * * @p_hwfn: HW device data. * @p_aeu: Descriptor of an AEU bit which caused the parity. * @aeu_en_reg: Address of the AEU enable register. * @bit_index: Index (0-31) of an AEU bit. */ static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, struct aeu_invert_reg_bit *p_aeu, u32 aeu_en_reg, u8 bit_index) { … } /** * qed_int_deassertion() - Handle deassertion of previously asserted * attentions. * * @p_hwfn: HW device data. * @deasserted_bits: newly deasserted bits. * * Return: Zero value. */ static int qed_int_deassertion(struct qed_hwfn *p_hwfn, u16 deasserted_bits) { … } static int qed_int_attentions(struct qed_hwfn *p_hwfn) { … } static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, void __iomem *igu_addr, u32 ack_cons) { … } void qed_int_sp_dpc(struct tasklet_struct *t) { … } static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) { … } static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, void *sb_virt_addr, dma_addr_t sb_phy_addr) { … } static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } /* coalescing timeout = timeset << (timer_res + 1) */ #define QED_CAU_DEF_RX_USECS … #define QED_CAU_DEF_TX_USECS … void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, struct cau_sb_entry *p_sb_entry, u8 pf_id, u16 vf_number, u8 vf_valid) { … } static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 igu_sb_id, u32 pi_index, enum qed_coalescing_fsm coalescing_fsm, u8 timeset) { … } void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, dma_addr_t sb_phys, u16 igu_sb_id, u16 vf_number, u8 vf_valid) { … } void qed_int_sb_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) { … } struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) { … } static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) { … } u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) { … } int qed_int_sb_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct qed_sb_info *sb_info, void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) { … } int qed_int_sb_release(struct qed_hwfn *p_hwfn, struct qed_sb_info *sb_info, u16 sb_id) { … } static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) { … } static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } int qed_int_register_cb(struct qed_hwfn *p_hwfn, qed_int_comp_cb_t comp_cb, void *cookie, u8 *sb_idx, __le16 **p_fw_cons) { … } int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) { … } u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) { … } void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, enum qed_int_mode int_mode) { … } static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, enum qed_int_mode int_mode) { … } void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } #define IGU_CLEANUP_SLEEP_LENGTH … static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 igu_sb_id, bool cleanup_set, u16 opaque_fid) { … } void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 igu_sb_id, u16 opaque, bool b_set) { … } void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_set, bool b_slowpath) { … } int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 igu_sb_id) { … } int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } /** * qed_int_igu_init_rt() - Initialize IGU runtime registers. * * @p_hwfn: HW device data. */ void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) { … } u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) { … } static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) { … } int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } void qed_int_free(struct qed_hwfn *p_hwfn) { … } void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) { … } void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, struct qed_sb_cnt_info *p_sb_cnt_info) { … } void qed_int_disable_post_isr_release(struct qed_dev *cdev) { … } void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) { … } int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u8 timer_res, u16 sb_id, bool tx) { … } int qed_int_get_sb_dbg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, struct qed_sb_info *p_sb, struct qed_sb_info_dbg *p_info) { … }
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