linux/drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
 */

/* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
 */

#include <linux/iopoll.h>
#include "emac.h"

/* EMAC_SGMII register offsets */
#define EMAC_SGMII_PHY_TX_PWR_CTRL …
#define EMAC_SGMII_PHY_LANE_CTRL1 …
#define EMAC_SGMII_PHY_CDR_CTRL0 …
#define EMAC_SGMII_PHY_POW_DWN_CTRL0 …
#define EMAC_SGMII_PHY_RESET_CTRL …
#define EMAC_SGMII_PHY_INTERRUPT_MASK …

/* SGMII digital lane registers */
#define EMAC_SGMII_LN_DRVR_CTRL0 …
#define EMAC_SGMII_LN_DRVR_TAP_EN …
#define EMAC_SGMII_LN_TX_MARGINING …
#define EMAC_SGMII_LN_TX_PRE …
#define EMAC_SGMII_LN_TX_POST …
#define EMAC_SGMII_LN_TX_BAND_MODE …
#define EMAC_SGMII_LN_LANE_MODE …
#define EMAC_SGMII_LN_PARALLEL_RATE …
#define EMAC_SGMII_LN_CML_CTRL_MODE0 …
#define EMAC_SGMII_LN_MIXER_CTRL_MODE0 …
#define EMAC_SGMII_LN_VGA_INITVAL …
#define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 …
#define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 …
#define EMAC_SGMII_LN_UCDR_SO_CONFIG …
#define EMAC_SGMII_LN_RX_BAND …
#define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 …
#define EMAC_SGMII_LN_RSM_CONFIG …
#define EMAC_SGMII_LN_SIGDET_ENABLES …
#define EMAC_SGMII_LN_SIGDET_CNTRL …
#define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL …
#define EMAC_SGMII_LN_RX_EN_SIGNAL …
#define EMAC_SGMII_LN_RX_MISC_CNTRL0 …
#define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV …

/* SGMII digital lane register values */
#define UCDR_STEP_BY_TWO_MODE0 …
#define UCDR_xO_GAIN_MODE(x) …
#define UCDR_ENABLE …
#define UCDR_SO_SATURATION(x) …

#define SIGDET_LP_BYP_PS4 …
#define SIGDET_EN_PS0_TO_PS2 …

#define TXVAL_VALID_INIT …
#define KR_PCIGEN3_MODE …

#define MAIN_EN …

#define TX_MARGINING_MUX …
#define TX_MARGINING(x) …

#define TX_PRE_MUX …

#define TX_POST_MUX …

#define CML_GEAR_MODE(x) …
#define CML2CMOS_IBOOST_MODE(x) …

#define MIXER_LOADB_MODE(x) …
#define MIXER_DATARATE_MODE(x) …

#define VGA_THRESH_DFE(x) …

#define SIGDET_LP_BYP_PS0_TO_PS2 …
#define SIGDET_FLT_BYP …

#define SIGDET_LVL(x) …

#define SIGDET_DEGLITCH_CTRL(x) …

#define DRVR_LOGIC_CLK_EN …
#define DRVR_LOGIC_CLK_DIV(x) …

#define PARALLEL_RATE_MODE0(x) …

#define BAND_MODE0(x) …

#define LANE_MODE(x) …

#define CDR_PD_SEL_MODE0(x) …
#define BYPASS_RSM_SAMP_CAL …
#define BYPASS_RSM_DLL_CAL …

#define L0_RX_EQUALIZE_ENABLE …

#define PWRDN_B …

#define CDR_MAX_CNT(x) …

#define SERDES_START_WAIT_TIMES …

struct emac_reg_write { … };

static void emac_reg_write_all(void __iomem *base,
			       const struct emac_reg_write *itr, size_t size)
{ … }

static const struct emac_reg_write sgmii_laned[] = …;

static const struct emac_reg_write physical_coding_sublayer_programming[] = …;

int emac_sgmii_init_qdf2432(struct emac_adapter *adpt)
{ … }