linux/drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
 */

/* Qualcomm Technologies, Inc. FSM9900 EMAC SGMII Controller driver.
 */

#include <linux/iopoll.h>
#include "emac.h"

/* EMAC_QSERDES register offsets */
#define EMAC_QSERDES_COM_SYS_CLK_CTRL …
#define EMAC_QSERDES_COM_PLL_CNTRL …
#define EMAC_QSERDES_COM_PLL_IP_SETI …
#define EMAC_QSERDES_COM_PLL_CP_SETI …
#define EMAC_QSERDES_COM_PLL_IP_SETP …
#define EMAC_QSERDES_COM_PLL_CP_SETP …
#define EMAC_QSERDES_COM_SYSCLK_EN_SEL …
#define EMAC_QSERDES_COM_RESETSM_CNTRL …
#define EMAC_QSERDES_COM_PLLLOCK_CMP1 …
#define EMAC_QSERDES_COM_PLLLOCK_CMP2 …
#define EMAC_QSERDES_COM_PLLLOCK_CMP3 …
#define EMAC_QSERDES_COM_PLLLOCK_CMP_EN …
#define EMAC_QSERDES_COM_DEC_START1 …
#define EMAC_QSERDES_COM_DIV_FRAC_START1 …
#define EMAC_QSERDES_COM_DIV_FRAC_START2 …
#define EMAC_QSERDES_COM_DIV_FRAC_START3 …
#define EMAC_QSERDES_COM_DEC_START2 …
#define EMAC_QSERDES_COM_PLL_CRCTRL …
#define EMAC_QSERDES_COM_RESET_SM …
#define EMAC_QSERDES_TX_BIST_MODE_LANENO …
#define EMAC_QSERDES_TX_TX_EMP_POST1_LVL …
#define EMAC_QSERDES_TX_TX_DRV_LVL …
#define EMAC_QSERDES_TX_LANE_MODE …
#define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN …
#define EMAC_QSERDES_RX_CDR_CONTROL …
#define EMAC_QSERDES_RX_CDR_CONTROL2 …
#define EMAC_QSERDES_RX_RX_EQ_GAIN12 …

/* EMAC_SGMII register offsets */
#define EMAC_SGMII_PHY_SERDES_START …
#define EMAC_SGMII_PHY_CMN_PWR_CTRL …
#define EMAC_SGMII_PHY_RX_PWR_CTRL …
#define EMAC_SGMII_PHY_TX_PWR_CTRL …
#define EMAC_SGMII_PHY_LANE_CTRL1 …
#define EMAC_SGMII_PHY_CDR_CTRL0 …
#define EMAC_SGMII_PHY_POW_DWN_CTRL0 …
#define EMAC_SGMII_PHY_INTERRUPT_MASK …

#define PLL_IPSETI(x) …

#define PLL_CPSETI(x) …

#define PLL_IPSETP(x) …

#define PLL_CPSETP(x) …

#define PLL_RCTRL(x) …
#define PLL_CCTRL(x) …

#define LANE_MODE(x) …

#define SYSCLK_CM …
#define SYSCLK_AC_COUPLE …

#define OCP_EN …
#define PLL_DIV_FFEN …
#define PLL_DIV_ORD …

#define SYSCLK_SEL_CMOS …

#define FRQ_TUNE_MODE …

#define PLLLOCK_CMP_EN …

#define DEC_START1_MUX …
#define DEC_START1(x) …

#define DIV_FRAC_START_MUX …
#define DIV_FRAC_START(x) …

#define DIV_FRAC_START3_MUX …
#define DIV_FRAC_START3(x) …

#define DEC_START2_MUX …
#define DEC_START2 …

#define READY …

#define TX_EMP_POST1_LVL_MUX …
#define TX_EMP_POST1_LVL(x) …

#define TX_DRV_LVL_MUX …
#define TX_DRV_LVL(x) …

#define EMP_EN_MUX …
#define EMP_EN …

#define SECONDORDERENABLE …
#define FIRSTORDER_THRESH(x) …
#define SECONDORDERGAIN(x) …

#define RX_EQ_GAIN2(x) …
#define RX_EQ_GAIN1(x) …

#define SERDES_START …

#define BIAS_EN …
#define PLL_EN …
#define SYSCLK_EN …
#define CLKBUF_L_EN …
#define PLL_TXCLK_EN …
#define PLL_RXCLK_EN …

#define L0_RX_SIGDET_EN …
#define L0_RX_TERM_MODE(x) …
#define L0_RX_I_EN …

#define L0_TX_EN …
#define L0_CLKBUF_EN …
#define L0_TRAN_BIAS_EN …

#define L0_RX_EQUALIZE_ENABLE …
#define L0_RESET_TSYNC_EN …
#define L0_DRV_LVL(x) …

#define PWRDN_B …
#define CDR_MAX_CNT(x) …

#define PLLLOCK_CMP(x) …

#define SERDES_START_WAIT_TIMES …

struct emac_reg_write { … };

static void emac_reg_write_all(void __iomem *base,
			       const struct emac_reg_write *itr, size_t size)
{ … }

static const struct emac_reg_write physical_coding_sublayer_programming[] = …;

static const struct emac_reg_write sysclk_refclk_setting[] = …;

static const struct emac_reg_write pll_setting[] = …;

static const struct emac_reg_write cdr_setting[] = …;

static const struct emac_reg_write tx_rx_setting[] = …;

int emac_sgmii_init_fsm9900(struct emac_adapter *adpt)
{ … }