/* SPDX-License-Identifier: GPL-2.0-only */ /* 10G controller driver for Samsung SoCs * * Copyright (C) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Author: Siva Reddy Kallam <[email protected]> */ #ifndef __SXGBE_COMMON_H__ #define __SXGBE_COMMON_H__ /* forward references */ struct sxgbe_desc_ops; struct sxgbe_dma_ops; struct sxgbe_mtl_ops; #define SXGBE_RESOURCE_NAME … #define DRV_MODULE_VERSION … /* MAX HW feature words */ #define SXGBE_HW_WORDS … #define SXGBE_RX_COE_NONE … /* CSR Frequency Access Defines*/ #define SXGBE_CSR_F_150M … #define SXGBE_CSR_F_250M … #define SXGBE_CSR_F_300M … #define SXGBE_CSR_F_350M … #define SXGBE_CSR_F_400M … #define SXGBE_CSR_F_500M … /* pause time */ #define SXGBE_PAUSE_TIME … /* tx queues */ #define SXGBE_TX_QUEUES … #define SXGBE_RX_QUEUES … /* Calculated based how much time does it take to fill 256KB Rx memory * at 10Gb speed at 156MHz clock rate and considered little less then * the actual value. */ #define SXGBE_MAX_DMA_RIWT … #define SXGBE_MIN_DMA_RIWT … /* Tx coalesce parameters */ #define SXGBE_COAL_TX_TIMER … #define SXGBE_MAX_COAL_TX_TICK … #define SXGBE_TX_MAX_FRAMES … #define SXGBE_TX_FRAMES … /* SXGBE TX FIFO is 8K, Rx FIFO is 16K */ #define BUF_SIZE_16KiB … #define BUF_SIZE_8KiB … #define BUF_SIZE_4KiB … #define BUF_SIZE_2KiB … #define SXGBE_DEFAULT_LIT_LS … #define SXGBE_DEFAULT_TWT_LS … /* Flow Control defines */ #define SXGBE_FLOW_OFF … #define SXGBE_FLOW_RX … #define SXGBE_FLOW_TX … #define SXGBE_FLOW_AUTO … #define SF_DMA_MODE … /* errors */ #define RX_GMII_ERR … #define RX_WATCHDOG_ERR … #define RX_CRC_ERR … #define RX_GAINT_ERR … #define RX_IP_HDR_ERR … #define RX_PAYLOAD_ERR … #define RX_OVERFLOW_ERR … /* pkt type */ #define RX_LEN_PKT … #define RX_MACCTL_PKT … #define RX_DCBCTL_PKT … #define RX_ARP_PKT … #define RX_OAM_PKT … #define RX_UNTAG_PKT … #define RX_OTHER_PKT … #define RX_SVLAN_PKT … #define RX_CVLAN_PKT … #define RX_DVLAN_OCVLAN_ICVLAN_PKT … #define RX_DVLAN_OSVLAN_ISVLAN_PKT … #define RX_DVLAN_OSVLAN_ICVLAN_PKT … #define RX_DVLAN_OCVLAN_ISVLAN_PKT … #define RX_NOT_IP_PKT … #define RX_IPV4_TCP_PKT … #define RX_IPV4_UDP_PKT … #define RX_IPV4_ICMP_PKT … #define RX_IPV4_UNKNOWN_PKT … #define RX_IPV6_TCP_PKT … #define RX_IPV6_UDP_PKT … #define RX_IPV6_ICMP_PKT … #define RX_IPV6_UNKNOWN_PKT … #define RX_NO_PTP … #define RX_PTP_SYNC … #define RX_PTP_FOLLOW_UP … #define RX_PTP_DELAY_REQ … #define RX_PTP_DELAY_RESP … #define RX_PTP_PDELAY_REQ … #define RX_PTP_PDELAY_RESP … #define RX_PTP_PDELAY_FOLLOW_UP … #define RX_PTP_ANNOUNCE … #define RX_PTP_MGMT … #define RX_PTP_SIGNAL … #define RX_PTP_RESV_MSG … /* EEE-LPI mode flags*/ #define TX_ENTRY_LPI_MODE … #define TX_EXIT_LPI_MODE … #define RX_ENTRY_LPI_MODE … #define RX_EXIT_LPI_MODE … /* EEE-LPI Interrupt status flag */ #define LPI_INT_STATUS … /* EEE-LPI Default timer values */ #define LPI_LINK_STATUS_TIMER … #define LPI_MAC_WAIT_TIMER … /* EEE-LPI Control and status definitions */ #define LPI_CTRL_STATUS_TXA … #define LPI_CTRL_STATUS_PLSDIS … #define LPI_CTRL_STATUS_PLS … #define LPI_CTRL_STATUS_LPIEN … #define LPI_CTRL_STATUS_TXRSTP … #define LPI_CTRL_STATUS_RXRSTP … #define LPI_CTRL_STATUS_RLPIST … #define LPI_CTRL_STATUS_TLPIST … #define LPI_CTRL_STATUS_RLPIEX … #define LPI_CTRL_STATUS_RLPIEN … #define LPI_CTRL_STATUS_TLPIEX … #define LPI_CTRL_STATUS_TLPIEN … enum dma_irq_status { … }; #define NETIF_F_HW_VLAN_ALL … /* MMC control defines */ #define SXGBE_MMC_CTRL_CNT_FRZ … /* SXGBE HW ADDR regs */ #define SXGBE_ADDR_HIGH(reg) … #define SXGBE_ADDR_LOW(reg) … #define SXGBE_MAX_PERFECT_ADDRESSES … #define SXGBE_FRAME_FILTER … /* SXGBE Frame Filter defines */ #define SXGBE_FRAME_FILTER_PR … #define SXGBE_FRAME_FILTER_HUC … #define SXGBE_FRAME_FILTER_HMC … #define SXGBE_FRAME_FILTER_DAIF … #define SXGBE_FRAME_FILTER_PM … #define SXGBE_FRAME_FILTER_DBF … #define SXGBE_FRAME_FILTER_SAIF … #define SXGBE_FRAME_FILTER_SAF … #define SXGBE_FRAME_FILTER_HPF … #define SXGBE_FRAME_FILTER_RA … #define SXGBE_HASH_TABLE_SIZE … #define SXGBE_HASH_HIGH … #define SXGBE_HASH_LOW … #define SXGBE_HI_REG_AE … /* Minimum and maximum MTU */ #define MIN_MTU … #define MAX_MTU … #define SXGBE_FOR_EACH_QUEUE(max_queues, queue_num) … #define DRV_VERSION … #define SXGBE_MAX_RX_CHANNELS … #define SXGBE_MAX_TX_CHANNELS … #define START_MAC_REG_OFFSET … #define MAX_MAC_REG_OFFSET … #define START_MTL_REG_OFFSET … #define MAX_MTL_REG_OFFSET … #define START_DMA_REG_OFFSET … #define MAX_DMA_REG_OFFSET … #define REG_SPACE_SIZE … /* sxgbe statistics counters */ struct sxgbe_extra_stats { … }; struct mac_link { … }; struct mii_regs { … }; struct sxgbe_core_ops { … }; const struct sxgbe_core_ops *sxgbe_get_core_ops(void); struct sxgbe_ops { … }; /* SXGBE private data structures */ struct sxgbe_tx_queue { … }; struct sxgbe_rx_queue { … }; /* SXGBE HW capabilities */ struct sxgbe_hw_features { … }; struct sxgbe_priv_data { … }; /* Function prototypes */ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device, struct sxgbe_plat_data *plat_dat, void __iomem *addr); void sxgbe_drv_remove(struct net_device *ndev); void sxgbe_set_ethtool_ops(struct net_device *netdev); int sxgbe_mdio_unregister(struct net_device *ndev); int sxgbe_mdio_register(struct net_device *ndev); int sxgbe_register_platform(void); void sxgbe_unregister_platform(void); #ifdef CONFIG_PM int sxgbe_suspend(struct net_device *ndev); int sxgbe_resume(struct net_device *ndev); int sxgbe_freeze(struct net_device *ndev); int sxgbe_restore(struct net_device *ndev); #endif /* CONFIG_PM */ const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void); void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv); bool sxgbe_eee_init(struct sxgbe_priv_data * const priv); #endif /* __SXGBE_COMMON_H__ */
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