/* SPDX-License-Identifier: GPL-2.0-only */ /* 10G controller driver for Samsung SoCs * * Copyright (C) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Author: Siva Reddy Kallam <[email protected]> */ #ifndef __SXGBE_REGMAP_H__ #define __SXGBE_REGMAP_H__ /* SXGBE MAC Registers */ #define SXGBE_CORE_TX_CONFIG_REG … #define SXGBE_CORE_RX_CONFIG_REG … #define SXGBE_CORE_PKT_FILTER_REG … #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG … #define SXGBE_CORE_HASH_TABLE_REG0 … #define SXGBE_CORE_HASH_TABLE_REG1 … #define SXGBE_CORE_HASH_TABLE_REG2 … #define SXGBE_CORE_HASH_TABLE_REG3 … #define SXGBE_CORE_HASH_TABLE_REG4 … #define SXGBE_CORE_HASH_TABLE_REG5 … #define SXGBE_CORE_HASH_TABLE_REG6 … #define SXGBE_CORE_HASH_TABLE_REG7 … /* EEE-LPI Registers */ #define SXGBE_CORE_LPI_CTRL_STATUS … #define SXGBE_CORE_LPI_TIMER_CTRL … /* VLAN Specific Registers */ #define SXGBE_CORE_VLAN_TAG_REG … #define SXGBE_CORE_VLAN_HASHTAB_REG … #define SXGBE_CORE_VLAN_INSCTL_REG … #define SXGBE_CORE_VLAN_INNERCTL_REG … #define SXGBE_CORE_RX_ETHTYPE_MATCH_REG … /* Flow Contol Registers */ #define SXGBE_CORE_TX_Q0_FLOWCTL_REG … #define SXGBE_CORE_TX_Q1_FLOWCTL_REG … #define SXGBE_CORE_TX_Q2_FLOWCTL_REG … #define SXGBE_CORE_TX_Q3_FLOWCTL_REG … #define SXGBE_CORE_TX_Q4_FLOWCTL_REG … #define SXGBE_CORE_TX_Q5_FLOWCTL_REG … #define SXGBE_CORE_TX_Q6_FLOWCTL_REG … #define SXGBE_CORE_TX_Q7_FLOWCTL_REG … #define SXGBE_CORE_RX_FLOWCTL_REG … #define SXGBE_CORE_RX_CTL0_REG … #define SXGBE_CORE_RX_CTL1_REG … #define SXGBE_CORE_RX_CTL2_REG … #define SXGBE_CORE_RX_CTL3_REG … #define SXGBE_CORE_RXQ_ENABLE_MASK … #define SXGBE_CORE_RXQ_ENABLE … #define SXGBE_CORE_RXQ_DISABLE … /* Interrupt Registers */ #define SXGBE_CORE_INT_STATUS_REG … #define SXGBE_CORE_INT_ENABLE_REG … #define SXGBE_CORE_RXTX_ERR_STATUS_REG … #define SXGBE_CORE_PMT_CTL_STATUS_REG … #define SXGBE_CORE_RWK_PKT_FILTER_REG … #define SXGBE_CORE_VERSION_REG … #define SXGBE_CORE_DEBUG_REG … #define SXGBE_CORE_HW_FEA_REG(index) … /* SMA(MDIO) module registers */ #define SXGBE_MDIO_SCMD_ADD_REG … #define SXGBE_MDIO_SCMD_DATA_REG … #define SXGBE_MDIO_CCMD_WADD_REG … #define SXGBE_MDIO_CCMD_WDATA_REG … #define SXGBE_MDIO_CSCAN_PORT_REG … #define SXGBE_MDIO_INT_STATUS_REG … #define SXGBE_MDIO_INT_ENABLE_REG … #define SXGBE_MDIO_PORT_CONDCON_REG … #define SXGBE_MDIO_CLAUSE22_PORT_REG … /* port specific, addr = 0-3 */ #define SXGBE_MDIO_DEV_BASE_REG … #define SXGBE_MDIO_PORT_DEV_REG(addr) … #define SXGBE_MDIO_PORT_LSTATUS_REG(addr) … #define SXGBE_MDIO_PORT_ALIVE_REG(addr) … #define SXGBE_CORE_GPIO_CTL_REG … #define SXGBE_CORE_GPIO_STATUS_REG … /* Address registers for filtering */ #define SXGBE_CORE_ADD_BASE_REG … /* addr = 0-31 */ #define SXGBE_CORE_ADD_HIGHOFFSET(addr) … #define SXGBE_CORE_ADD_LOWOFFSET(addr) … /* SXGBE MMC registers */ #define SXGBE_MMC_CTL_REG … #define SXGBE_MMC_RXINT_STATUS_REG … #define SXGBE_MMC_TXINT_STATUS_REG … #define SXGBE_MMC_RXINT_ENABLE_REG … #define SXGBE_MMC_TXINT_ENABLE_REG … /* TX specific counters */ #define SXGBE_MMC_TXOCTETHI_GBCNT_REG … #define SXGBE_MMC_TXOCTETLO_GBCNT_REG … #define SXGBE_MMC_TXFRAMELO_GBCNT_REG … #define SXGBE_MMC_TXFRAMEHI_GBCNT_REG … #define SXGBE_MMC_TXBROADLO_GCNT_REG … #define SXGBE_MMC_TXBROADHI_GCNT_REG … #define SXGBE_MMC_TXMULTILO_GCNT_REG … #define SXGBE_MMC_TXMULTIHI_GCNT_REG … #define SXGBE_MMC_TX64LO_GBCNT_REG … #define SXGBE_MMC_TX64HI_GBCNT_REG … #define SXGBE_MMC_TX65TO127LO_GBCNT_REG … #define SXGBE_MMC_TX65TO127HI_GBCNT_REG … #define SXGBE_MMC_TX128TO255LO_GBCNT_REG … #define SXGBE_MMC_TX128TO255HI_GBCNT_REG … #define SXGBE_MMC_TX256TO511LO_GBCNT_REG … #define SXGBE_MMC_TX256TO511HI_GBCNT_REG … #define SXGBE_MMC_TX512TO1023LO_GBCNT_REG … #define SXGBE_MMC_TX512TO1023HI_GBCNT_REG … #define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG … #define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG … #define SXGBE_MMC_TXUNICASTLO_GBCNT_REG … #define SXGBE_MMC_TXUNICASTHI_GBCNT_REG … #define SXGBE_MMC_TXMULTILO_GBCNT_REG … #define SXGBE_MMC_TXMULTIHI_GBCNT_REG … #define SXGBE_MMC_TXBROADLO_GBCNT_REG … #define SXGBE_MMC_TXBROADHI_GBCNT_REG … #define SXGBE_MMC_TXUFLWLO_GBCNT_REG … #define SXGBE_MMC_TXUFLWHI_GBCNT_REG … #define SXGBE_MMC_TXOCTETLO_GCNT_REG … #define SXGBE_MMC_TXOCTETHI_GCNT_REG … #define SXGBE_MMC_TXFRAMELO_GCNT_REG … #define SXGBE_MMC_TXFRAMEHI_GCNT_REG … #define SXGBE_MMC_TXPAUSELO_CNT_REG … #define SXGBE_MMC_TXPAUSEHI_CNT_REG … #define SXGBE_MMC_TXVLANLO_GCNT_REG … #define SXGBE_MMC_TXVLANHI_GCNT_REG … /* RX specific counters */ #define SXGBE_MMC_RXFRAMELO_GBCNT_REG … #define SXGBE_MMC_RXFRAMEHI_GBCNT_REG … #define SXGBE_MMC_RXOCTETLO_GBCNT_REG … #define SXGBE_MMC_RXOCTETHI_GBCNT_REG … #define SXGBE_MMC_RXOCTETLO_GCNT_REG … #define SXGBE_MMC_RXOCTETHI_GCNT_REG … #define SXGBE_MMC_RXBROADLO_GCNT_REG … #define SXGBE_MMC_RXBROADHI_GCNT_REG … #define SXGBE_MMC_RXMULTILO_GCNT_REG … #define SXGBE_MMC_RXMULTIHI_GCNT_REG … #define SXGBE_MMC_RXCRCERRLO_REG … #define SXGBE_MMC_RXCRCERRHI_REG … #define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG … #define SXGBE_MMC_RXJABBERERR_REG … #define SXGBE_MMC_RXSHORT64BFRAME_COR_REG … #define SXGBE_MMC_RXOVERMAXFRAME_COR_REG … #define SXGBE_MMC_RX64LO_GBCNT_REG … #define SXGBE_MMC_RX64HI_GBCNT_REG … #define SXGBE_MMC_RX65TO127LO_GBCNT_REG … #define SXGBE_MMC_RX65TO127HI_GBCNT_REG … #define SXGBE_MMC_RX128TO255LO_GBCNT_REG … #define SXGBE_MMC_RX128TO255HI_GBCNT_REG … #define SXGBE_MMC_RX256TO511LO_GBCNT_REG … #define SXGBE_MMC_RX256TO511HI_GBCNT_REG … #define SXGBE_MMC_RX512TO1023LO_GBCNT_REG … #define SXGBE_MMC_RX512TO1023HI_GBCNT_REG … #define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG … #define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG … #define SXGBE_MMC_RXUNICASTLO_GCNT_REG … #define SXGBE_MMC_RXUNICASTHI_GCNT_REG … #define SXGBE_MMC_RXLENERRLO_REG … #define SXGBE_MMC_RXLENERRHI_REG … #define SXGBE_MMC_RXOUTOFRANGETYPELO_REG … #define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG … #define SXGBE_MMC_RXPAUSELO_CNT_REG … #define SXGBE_MMC_RXPAUSEHI_CNT_REG … #define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG … #define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG … #define SXGBE_MMC_RXVLANLO_GBCNT_REG … #define SXGBE_MMC_RXVLANHI_GBCNT_REG … #define SXGBE_MMC_RXWATCHDOG_ERR_REG … /* L3/L4 function registers */ #define SXGBE_CORE_L34_ADDCTL_REG … #define SXGBE_CORE_L34_DATA_REG … /* ARP registers */ #define SXGBE_CORE_ARP_ADD_REG … /* RSS registers */ #define SXGBE_CORE_RSS_CTL_REG … #define SXGBE_CORE_RSS_ADD_REG … #define SXGBE_CORE_RSS_DATA_REG … /* RSS control register bits */ #define SXGBE_CORE_RSS_CTL_UDP4TE … #define SXGBE_CORE_RSS_CTL_TCP4TE … #define SXGBE_CORE_RSS_CTL_IP2TE … #define SXGBE_CORE_RSS_CTL_RSSE … /* IEEE 1588 registers */ #define SXGBE_CORE_TSTAMP_CTL_REG … #define SXGBE_CORE_SUBSEC_INC_REG … #define SXGBE_CORE_SYSTIME_SEC_REG … #define SXGBE_CORE_SYSTIME_NSEC_REG … #define SXGBE_CORE_SYSTIME_SECUP_REG … #define SXGBE_CORE_TSTAMP_ADD_REG … #define SXGBE_CORE_SYSTIME_HWORD_REG … #define SXGBE_CORE_TSTAMP_STATUS_REG … #define SXGBE_CORE_TXTIME_STATUSNSEC_REG … #define SXGBE_CORE_TXTIME_STATUSSEC_REG … /* Auxiliary registers */ #define SXGBE_CORE_AUX_CTL_REG … #define SXGBE_CORE_AUX_TSTAMP_NSEC_REG … #define SXGBE_CORE_AUX_TSTAMP_SEC_REG … #define SXGBE_CORE_AUX_TSTAMP_INGCOR_REG … #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_REG … #define SXGBE_CORE_AUX_TSTAMP_INGCOR_NSEC_REG … #define SXGBE_CORE_AUX_TSTAMP_INGCOR_SUBNSEC_REG … #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_NSEC_REG … #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_SUBNSEC_REG … /* PPS registers */ #define SXGBE_CORE_PPS_CTL_REG … #define SXGBE_CORE_PPS_BASE … /* addr = 0 - 3 */ #define SXGBE_CORE_PPS_TTIME_SEC_REG(addr) … #define SXGBE_CORE_PPS_TTIME_NSEC_REG(addr) … #define SXGBE_CORE_PPS_INTERVAL_REG(addr) … #define SXGBE_CORE_PPS_WIDTH_REG(addr) … #define SXGBE_CORE_PTO_CTL_REG … #define SXGBE_CORE_SRCPORT_ITY0_REG … #define SXGBE_CORE_SRCPORT_ITY1_REG … #define SXGBE_CORE_SRCPORT_ITY2_REG … #define SXGBE_CORE_LOGMSG_LEVEL_REG … /* SXGBE MTL Registers */ #define SXGBE_MTL_BASE_REG … #define SXGBE_MTL_OP_MODE_REG … #define SXGBE_MTL_DEBUG_CTL_REG … #define SXGBE_MTL_DEBUG_STATUS_REG … #define SXGBE_MTL_FIFO_DEBUGDATA_REG … #define SXGBE_MTL_INT_STATUS_REG … #define SXGBE_MTL_RXQ_DMAMAP0_REG … #define SXGBE_MTL_RXQ_DMAMAP1_REG … #define SXGBE_MTL_RXQ_DMAMAP2_REG … #define SXGBE_MTL_TX_PRTYMAP0_REG … #define SXGBE_MTL_TX_PRTYMAP1_REG … /* TC/Queue registers, qnum=0-15 */ #define SXGBE_MTL_TC_TXBASE_REG … #define SXGBE_MTL_TXQ_OPMODE_REG(qnum) … #define SXGBE_MTL_SFMODE … #define SXGBE_MTL_FIFO_LSHIFT … #define SXGBE_MTL_ENABLE_QUEUE … #define SXGBE_MTL_TXQ_UNDERFLOW_REG(qnum) … #define SXGBE_MTL_TXQ_DEBUG_REG(qnum) … #define SXGBE_MTL_TXQ_ETSCTL_REG(qnum) … #define SXGBE_MTL_TXQ_ETSSTATUS_REG(qnum) … #define SXGBE_MTL_TXQ_QUANTWEIGHT_REG(qnum) … #define SXGBE_MTL_TC_RXBASE_REG … #define SXGBE_RX_MTL_SFMODE … #define SXGBE_MTL_RXQ_OPMODE_REG(qnum) … #define SXGBE_MTL_RXQ_MISPKTOVERFLOW_REG(qnum) … #define SXGBE_MTL_RXQ_DEBUG_REG(qnum) … #define SXGBE_MTL_RXQ_CTL_REG(qnum) … #define SXGBE_MTL_RXQ_INTENABLE_REG(qnum) … #define SXGBE_MTL_RXQ_INTSTATUS_REG(qnum) … /* SXGBE DMA Registers */ #define SXGBE_DMA_BASE_REG … #define SXGBE_DMA_MODE_REG … #define SXGBE_DMA_SOFT_RESET … #define SXGBE_DMA_SYSBUS_MODE_REG … #define SXGBE_DMA_AXI_UNDEF_BURST … #define SXGBE_DMA_ENHACE_ADDR_MODE … #define SXGBE_DMA_INT_STATUS_REG … #define SXGBE_DMA_AXI_ARCACHECTL_REG … #define SXGBE_DMA_AXI_AWCACHECTL_REG … #define SXGBE_DMA_DEBUG_STATUS0_REG … #define SXGBE_DMA_DEBUG_STATUS1_REG … #define SXGBE_DMA_DEBUG_STATUS2_REG … #define SXGBE_DMA_DEBUG_STATUS3_REG … #define SXGBE_DMA_DEBUG_STATUS4_REG … #define SXGBE_DMA_DEBUG_STATUS5_REG … /* Channel Registers, cha_num = 0-15 */ #define SXGBE_DMA_CHA_BASE_REG … #define SXGBE_DMA_CHA_CTL_REG(cha_num) … #define SXGBE_DMA_PBL_X8MODE … #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE … #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) … #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) … #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) … #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) … #define SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num) … #define SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num) … #define SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num) … #define SXGBE_DMA_CHA_RXDESC_TAILPTR_REG(cha_num) … #define SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num) … #define SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num) … #define SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num) … #define SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(cha_num) … #define SXGBE_DMA_CHA_TXDESC_CURADDLO_REG(cha_num) … #define SXGBE_DMA_CHA_RXDESC_CURADDLO_REG(cha_num) … #define SXGBE_DMA_CHA_CURTXBUF_ADDHI_REG(cha_num) … #define SXGBE_DMA_CHA_CURTXBUF_ADDLO_REG(cha_num) … #define SXGBE_DMA_CHA_CURRXBUF_ADDHI_REG(cha_num) … #define SXGBE_DMA_CHA_CURRXBUF_ADDLO_REG(cha_num) … #define SXGBE_DMA_CHA_STATUS_REG(cha_num) … /* TX DMA control register specific */ #define SXGBE_TX_START_DMA … /* sxgbe tx configuration register bitfields */ #define SXGBE_SPEED_10G … #define SXGBE_SPEED_2_5G … #define SXGBE_SPEED_1G … #define SXGBE_SPEED_LSHIFT … #define SXGBE_TX_ENABLE … #define SXGBE_TX_DISDIC_ALGO … #define SXGBE_TX_JABBER_DISABLE … /* sxgbe rx configuration register bitfields */ #define SXGBE_RX_ENABLE … #define SXGBE_RX_ACS_ENABLE … #define SXGBE_RX_WATCHDOG_DISABLE … #define SXGBE_RX_JUMBPKT_ENABLE … #define SXGBE_RX_CSUMOFFLOAD_ENABLE … #define SXGBE_RX_LOOPBACK_ENABLE … #define SXGBE_RX_ARPOFFLOAD_ENABLE … /* sxgbe vlan Tag Register bitfields */ #define SXGBE_VLAN_SVLAN_ENABLE … #define SXGBE_VLAN_DOUBLEVLAN_ENABLE … #define SXGBE_VLAN_INNERVLAN_ENABLE … /* XMAC VLAN Tag Inclusion Register(0x0060) bitfields * Below fields same for Inner VLAN Tag Inclusion * Register(0x0064) register */ enum vlan_tag_ctl_tx { … }; #define SXGBE_VLAN_PRTY_CTL … #define SXGBE_VLAN_CSVL_CTL … /* SXGBE TX Q Flow Control Register bitfields */ #define SXGBE_TX_FLOW_CTL_FCB … #define SXGBE_TX_FLOW_CTL_TFB … /* SXGBE RX Q Flow Control Register bitfields */ #define SXGBE_RX_FLOW_CTL_ENABLE … #define SXGBE_RX_UNICAST_DETECT … #define SXGBE_RX_PRTYFLOW_CTL_ENABLE … /* sxgbe rx Q control0 register bitfields */ #define SXGBE_RX_Q_ENABLE … /* SXGBE hardware features bitfield specific */ /* Capability Register 0 */ #define SXGBE_HW_FEAT_GMII(cap) … #define SXGBE_HW_FEAT_VLAN_HASH_FILTER(cap) … #define SXGBE_HW_FEAT_SMA(cap) … #define SXGBE_HW_FEAT_PMT_TEMOTE_WOP(cap) … #define SXGBE_HW_FEAT_PMT_MAGIC_PKT(cap) … #define SXGBE_HW_FEAT_RMON(cap) … #define SXGBE_HW_FEAT_ARP_OFFLOAD(cap) … #define SXGBE_HW_FEAT_IEEE1500_2008(cap) … #define SXGBE_HW_FEAT_EEE(cap) … #define SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(cap) … #define SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(cap) … #define SXGBE_HW_FEAT_MACADDR_COUNT(cap) … #define SXGBE_HW_FEAT_TSTMAP_SRC(cap) … #define SXGBE_HW_FEAT_SRCADDR_VLAN(cap) … /* Capability Register 1 */ #define SXGBE_HW_FEAT_RX_FIFO_SIZE(cap) … #define SXGBE_HW_FEAT_TX_FIFO_SIZE(cap) … #define SXGBE_HW_FEAT_IEEE1588_HWORD(cap) … #define SXGBE_HW_FEAT_DCB(cap) … #define SXGBE_HW_FEAT_SPLIT_HDR(cap) … #define SXGBE_HW_FEAT_TSO(cap) … #define SXGBE_HW_FEAT_DEBUG_MEM_IFACE(cap) … #define SXGBE_HW_FEAT_RSS(cap) … #define SXGBE_HW_FEAT_HASH_TABLE_SIZE(cap) … #define SXGBE_HW_FEAT_L3L4_FILTER_NUM(cap) … /* Capability Register 2 */ #define SXGBE_HW_FEAT_RX_MTL_QUEUES(cap) … #define SXGBE_HW_FEAT_TX_MTL_QUEUES(cap) … #define SXGBE_HW_FEAT_RX_DMA_CHANNELS(cap) … #define SXGBE_HW_FEAT_TX_DMA_CHANNELS(cap) … #define SXGBE_HW_FEAT_PPS_OUTPUTS(cap) … #define SXGBE_HW_FEAT_AUX_SNAPSHOTS(cap) … /* DMAchannel interrupt enable specific */ /* DMA Normal interrupt */ #define SXGBE_DMA_INT_ENA_NIE … #define SXGBE_DMA_INT_ENA_TIE … #define SXGBE_DMA_INT_ENA_TUE … #define SXGBE_DMA_INT_ENA_RIE … #define SXGBE_DMA_INT_NORMAL … /* DMA Abnormal interrupt */ #define SXGBE_DMA_INT_ENA_AIE … #define SXGBE_DMA_INT_ENA_TSE … #define SXGBE_DMA_INT_ENA_RUE … #define SXGBE_DMA_INT_ENA_RSE … #define SXGBE_DMA_INT_ENA_FBE … #define SXGBE_DMA_INT_ENA_CDEE … #define SXGBE_DMA_INT_ABNORMAL … #define SXGBE_DMA_ENA_INT … /* DMA channel interrupt status specific */ #define SXGBE_DMA_INT_STATUS_REB2 … #define SXGBE_DMA_INT_STATUS_REB1 … #define SXGBE_DMA_INT_STATUS_REB0 … #define SXGBE_DMA_INT_STATUS_TEB2 … #define SXGBE_DMA_INT_STATUS_TEB1 … #define SXGBE_DMA_INT_STATUS_TEB0 … #define SXGBE_DMA_INT_STATUS_NIS … #define SXGBE_DMA_INT_STATUS_AIS … #define SXGBE_DMA_INT_STATUS_CTXTERR … #define SXGBE_DMA_INT_STATUS_FBE … #define SXGBE_DMA_INT_STATUS_RPS … #define SXGBE_DMA_INT_STATUS_RBU … #define SXGBE_DMA_INT_STATUS_RI … #define SXGBE_DMA_INT_STATUS_TBU … #define SXGBE_DMA_INT_STATUS_TPS … #define SXGBE_DMA_INT_STATUS_TI … #endif /* __SXGBE_REGMAP_H__ */
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