/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* Header File to describe the DMA descriptors and related definitions. This is for DWMAC100 and 1000 cores. Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __DESCS_H__ #define __DESCS_H__ #include <linux/bitops.h> /* Normal receive descriptor defines */ /* RDES0 */ #define RDES0_PAYLOAD_CSUM_ERR … #define RDES0_CRC_ERROR … #define RDES0_DRIBBLING … #define RDES0_MII_ERROR … #define RDES0_RECEIVE_WATCHDOG … #define RDES0_FRAME_TYPE … #define RDES0_COLLISION … #define RDES0_IPC_CSUM_ERROR … #define RDES0_LAST_DESCRIPTOR … #define RDES0_FIRST_DESCRIPTOR … #define RDES0_VLAN_TAG … #define RDES0_OVERFLOW_ERROR … #define RDES0_LENGTH_ERROR … #define RDES0_SA_FILTER_FAIL … #define RDES0_DESCRIPTOR_ERROR … #define RDES0_ERROR_SUMMARY … #define RDES0_FRAME_LEN_MASK … #define RDES0_FRAME_LEN_SHIFT … #define RDES0_DA_FILTER_FAIL … #define RDES0_OWN … /* RDES1 */ #define RDES1_BUFFER1_SIZE_MASK … #define RDES1_BUFFER2_SIZE_MASK … #define RDES1_BUFFER2_SIZE_SHIFT … #define RDES1_SECOND_ADDRESS_CHAINED … #define RDES1_END_RING … #define RDES1_DISABLE_IC … /* Enhanced receive descriptor defines */ /* RDES0 (similar to normal RDES) */ #define ERDES0_RX_MAC_ADDR … /* RDES1: completely differ from normal desc definitions */ #define ERDES1_BUFFER1_SIZE_MASK … #define ERDES1_SECOND_ADDRESS_CHAINED … #define ERDES1_END_RING … #define ERDES1_BUFFER2_SIZE_MASK … #define ERDES1_BUFFER2_SIZE_SHIFT … #define ERDES1_DISABLE_IC … /* Normal transmit descriptor defines */ /* TDES0 */ #define TDES0_DEFERRED … #define TDES0_UNDERFLOW_ERROR … #define TDES0_EXCESSIVE_DEFERRAL … #define TDES0_COLLISION_COUNT_MASK … #define TDES0_VLAN_FRAME … #define TDES0_EXCESSIVE_COLLISIONS … #define TDES0_LATE_COLLISION … #define TDES0_NO_CARRIER … #define TDES0_LOSS_CARRIER … #define TDES0_PAYLOAD_ERROR … #define TDES0_FRAME_FLUSHED … #define TDES0_JABBER_TIMEOUT … #define TDES0_ERROR_SUMMARY … #define TDES0_IP_HEADER_ERROR … #define TDES0_TIME_STAMP_STATUS … #define TDES0_OWN … /* TDES1 */ #define TDES1_BUFFER1_SIZE_MASK … #define TDES1_BUFFER2_SIZE_MASK … #define TDES1_BUFFER2_SIZE_SHIFT … #define TDES1_TIME_STAMP_ENABLE … #define TDES1_DISABLE_PADDING … #define TDES1_SECOND_ADDRESS_CHAINED … #define TDES1_END_RING … #define TDES1_CRC_DISABLE … #define TDES1_CHECKSUM_INSERTION_MASK … #define TDES1_CHECKSUM_INSERTION_SHIFT … #define TDES1_FIRST_SEGMENT … #define TDES1_LAST_SEGMENT … #define TDES1_INTERRUPT … /* Enhanced transmit descriptor defines */ /* TDES0 */ #define ETDES0_DEFERRED … #define ETDES0_UNDERFLOW_ERROR … #define ETDES0_EXCESSIVE_DEFERRAL … #define ETDES0_COLLISION_COUNT_MASK … #define ETDES0_VLAN_FRAME … #define ETDES0_EXCESSIVE_COLLISIONS … #define ETDES0_LATE_COLLISION … #define ETDES0_NO_CARRIER … #define ETDES0_LOSS_CARRIER … #define ETDES0_PAYLOAD_ERROR … #define ETDES0_FRAME_FLUSHED … #define ETDES0_JABBER_TIMEOUT … #define ETDES0_ERROR_SUMMARY … #define ETDES0_IP_HEADER_ERROR … #define ETDES0_TIME_STAMP_STATUS … #define ETDES0_SECOND_ADDRESS_CHAINED … #define ETDES0_END_RING … #define ETDES0_CHECKSUM_INSERTION_MASK … #define ETDES0_CHECKSUM_INSERTION_SHIFT … #define ETDES0_TIME_STAMP_ENABLE … #define ETDES0_DISABLE_PADDING … #define ETDES0_CRC_DISABLE … #define ETDES0_FIRST_SEGMENT … #define ETDES0_LAST_SEGMENT … #define ETDES0_INTERRUPT … #define ETDES0_OWN … /* TDES1 */ #define ETDES1_BUFFER1_SIZE_MASK … #define ETDES1_BUFFER2_SIZE_MASK … #define ETDES1_BUFFER2_SIZE_SHIFT … /* Extended Receive descriptor definitions */ #define ERDES4_IP_PAYLOAD_TYPE_MASK … #define ERDES4_IP_HDR_ERR … #define ERDES4_IP_PAYLOAD_ERR … #define ERDES4_IP_CSUM_BYPASSED … #define ERDES4_IPV4_PKT_RCVD … #define ERDES4_IPV6_PKT_RCVD … #define ERDES4_MSG_TYPE_MASK … #define ERDES4_PTP_FRAME_TYPE … #define ERDES4_PTP_VER … #define ERDES4_TIMESTAMP_DROPPED … #define ERDES4_AV_PKT_RCVD … #define ERDES4_AV_TAGGED_PKT_RCVD … #define ERDES4_VLAN_TAG_PRI_VAL_MASK … #define ERDES4_L3_FILTER_MATCH … #define ERDES4_L4_FILTER_MATCH … #define ERDES4_L3_L4_FILT_NO_MATCH_MASK … /* Extended RDES4 message type definitions */ #define RDES_EXT_NO_PTP … #define RDES_EXT_SYNC … #define RDES_EXT_FOLLOW_UP … #define RDES_EXT_DELAY_REQ … #define RDES_EXT_DELAY_RESP … #define RDES_EXT_PDELAY_REQ … #define RDES_EXT_PDELAY_RESP … #define RDES_EXT_PDELAY_FOLLOW_UP … #define RDES_PTP_ANNOUNCE … #define RDES_PTP_MANAGEMENT … #define RDES_PTP_SIGNALING … #define RDES_PTP_PKT_RESERVED_TYPE … /* Basic descriptor structure for normal and alternate descriptors */ struct dma_desc { … }; /* Extended descriptor structure (e.g. >= databook 3.50a) */ struct dma_extended_desc { … }; /* Enhanced descriptor for TBS */ struct dma_edesc { … }; /* Transmit checksum insertion control */ #define TX_CIC_FULL … #endif /* __DESCS_H__ */
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