/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* STMMAC Common Header File Copyright (C) 2007-2009 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __COMMON_H__ #define __COMMON_H__ #include <linux/etherdevice.h> #include <linux/netdevice.h> #include <linux/stmmac.h> #include <linux/phy.h> #include <linux/pcs/pcs-xpcs.h> #include <linux/module.h> #if IS_ENABLED(CONFIG_VLAN_8021Q) #define STMMAC_VLAN_TAG_USED #include <linux/if_vlan.h> #endif #include "descs.h" #include "hwif.h" #include "mmc.h" /* Synopsys Core versions */ #define DWMAC_CORE_3_40 … #define DWMAC_CORE_3_50 … #define DWMAC_CORE_4_00 … #define DWMAC_CORE_4_10 … #define DWMAC_CORE_5_00 … #define DWMAC_CORE_5_10 … #define DWMAC_CORE_5_20 … #define DWXGMAC_CORE_2_10 … #define DWXGMAC_CORE_2_20 … #define DWXLGMAC_CORE_2_00 … /* Device ID */ #define DWXGMAC_ID … #define DWXLGMAC_ID … #define STMMAC_CHAN0 … /* TX and RX Descriptor Length, these need to be power of two. * TX descriptor length less than 64 may cause transmit queue timed out error. * RX descriptor length less than 64 may cause inconsistent Rx chain error. */ #define DMA_MIN_TX_SIZE … #define DMA_MAX_TX_SIZE … #define DMA_DEFAULT_TX_SIZE … #define DMA_MIN_RX_SIZE … #define DMA_MAX_RX_SIZE … #define DMA_DEFAULT_RX_SIZE … #define STMMAC_GET_ENTRY(x, size) … #undef FRAME_FILTER_DEBUG /* #define FRAME_FILTER_DEBUG */ struct stmmac_q_tx_stats { … }; struct stmmac_napi_tx_stats { … }; struct stmmac_txq_stats { … } ____cacheline_aligned_in_smp; struct stmmac_napi_rx_stats { … }; struct stmmac_rxq_stats { … } ____cacheline_aligned_in_smp; /* Updates on each CPU protected by not allowing nested irqs. */ struct stmmac_pcpu_stats { … }; /* Extra statistic and debug information exposed by ethtool */ struct stmmac_extra_stats { … }; /* Safety Feature statistics exposed by ethtool */ struct stmmac_safety_stats { … }; /* Number of fields in Safety Stats */ #define STMMAC_SAFETY_FEAT_SIZE … /* CSR Frequency Access Defines*/ #define CSR_F_35M … #define CSR_F_60M … #define CSR_F_100M … #define CSR_F_150M … #define CSR_F_250M … #define CSR_F_300M … #define MAC_CSR_H_FRQ_MASK … #define HASH_TABLE_SIZE … #define PAUSE_TIME … /* Flow Control defines */ #define FLOW_OFF … #define FLOW_RX … #define FLOW_TX … #define FLOW_AUTO … /* PCS defines */ #define STMMAC_PCS_RGMII … #define STMMAC_PCS_SGMII … #define SF_DMA_MODE … /* DMA HW feature register fields */ #define DMA_HW_FEAT_MIISEL … #define DMA_HW_FEAT_GMIISEL … #define DMA_HW_FEAT_HDSEL … #define DMA_HW_FEAT_EXTHASHEN … #define DMA_HW_FEAT_HASHSEL … #define DMA_HW_FEAT_ADDMAC … #define DMA_HW_FEAT_PCSSEL … #define DMA_HW_FEAT_L3L4FLTREN … #define DMA_HW_FEAT_SMASEL … #define DMA_HW_FEAT_RWKSEL … #define DMA_HW_FEAT_MGKSEL … #define DMA_HW_FEAT_MMCSEL … #define DMA_HW_FEAT_TSVER1SEL … #define DMA_HW_FEAT_TSVER2SEL … #define DMA_HW_FEAT_EEESEL … #define DMA_HW_FEAT_AVSEL … #define DMA_HW_FEAT_TXCOESEL … #define DMA_HW_FEAT_RXTYP1COE … #define DMA_HW_FEAT_RXTYP2COE … #define DMA_HW_FEAT_RXFIFOSIZE … #define DMA_HW_FEAT_RXCHCNT … #define DMA_HW_FEAT_TXCHCNT … #define DMA_HW_FEAT_ENHDESSEL … /* Timestamping with Internal System Time */ #define DMA_HW_FEAT_INTTSEN … #define DMA_HW_FEAT_FLEXIPPSEN … #define DMA_HW_FEAT_SAVLANINS … #define DMA_HW_FEAT_ACTPHYIF … #define DEFAULT_DMA_PBL … /* MSI defines */ #define STMMAC_MSI_VEC_MAX … /* PCS status and mask defines */ #define PCS_ANE_IRQ … #define PCS_LINK_IRQ … #define PCS_RGSMIIIS_IRQ … /* Max/Min RI Watchdog Timer count value */ #define MAX_DMA_RIWT … #define MIN_DMA_RIWT … #define DEF_DMA_RIWT … /* Tx coalesce parameters */ #define STMMAC_COAL_TX_TIMER … #define STMMAC_MAX_COAL_TX_TICK … #define STMMAC_TX_MAX_FRAMES … #define STMMAC_TX_FRAMES … #define STMMAC_RX_FRAMES … /* Packets types */ enum packets_types { … }; /* Rx IPC status */ enum rx_frame_status { … }; /* Tx status */ enum tx_frame_status { … }; enum dma_irq_status { … }; enum dma_irq_dir { … }; enum request_irq_err { … }; /* EEE and LPI defines */ #define CORE_IRQ_TX_PATH_IN_LPI_MODE … #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE … #define CORE_IRQ_RX_PATH_IN_LPI_MODE … #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE … /* FPE defines */ #define FPE_EVENT_UNKNOWN … #define FPE_EVENT_TRSP … #define FPE_EVENT_TVER … #define FPE_EVENT_RRSP … #define FPE_EVENT_RVER … #define CORE_IRQ_MTL_RX_OVERFLOW … /* Physical Coding Sublayer */ struct rgmii_adv { … }; #define STMMAC_PCS_PAUSE … #define STMMAC_PCS_ASYM_PAUSE … /* DMA HW capabilities */ struct dma_features { … }; /* RX Buffer size must be multiple of 4/8/16 bytes */ #define BUF_SIZE_16KiB … #define BUF_SIZE_8KiB … #define BUF_SIZE_4KiB … #define BUF_SIZE_2KiB … /* Power Down and WOL */ #define PMT_NOT_SUPPORTED … #define PMT_SUPPORTED … /* Common MAC defines */ #define MAC_CTRL_REG … #define MAC_ENABLE_TX … #define MAC_ENABLE_RX … /* Default LPI timers */ #define STMMAC_DEFAULT_LIT_LS … #define STMMAC_DEFAULT_TWT_LS … #define STMMAC_ET_MAX … #define STMMAC_CHAIN_MODE … #define STMMAC_RING_MODE … #define JUMBO_LEN … /* Receive Side Scaling */ #define STMMAC_RSS_HASH_KEY_SIZE … #define STMMAC_RSS_MAX_TABLE_SIZE … /* VLAN */ #define STMMAC_VLAN_NONE … #define STMMAC_VLAN_REMOVE … #define STMMAC_VLAN_INSERT … #define STMMAC_VLAN_REPLACE … extern const struct stmmac_desc_ops enh_desc_ops; extern const struct stmmac_desc_ops ndesc_ops; struct mac_device_info; extern const struct stmmac_hwtimestamp stmmac_ptp; extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; struct mac_link { … }; struct mii_regs { … }; struct mac_device_info { … }; struct stmmac_rx_routing { … }; int dwmac100_setup(struct stmmac_priv *priv); int dwmac1000_setup(struct stmmac_priv *priv); int dwmac4_setup(struct stmmac_priv *priv); int dwxgmac2_setup(struct stmmac_priv *priv); int dwxlgmac2_setup(struct stmmac_priv *priv); void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low); void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low); void stmmac_set_mac(void __iomem *ioaddr, bool enable); void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low); void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low); void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); extern const struct stmmac_mode_ops ring_mode_ops; extern const struct stmmac_mode_ops chain_mode_ops; extern const struct stmmac_desc_ops dwmac4_desc_ops; #endif /* __COMMON_H__ */
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