/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* DWMAC DMA Header file. Copyright (C) 2007-2009 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __DWMAC_DMA_H__ #define __DWMAC_DMA_H__ /* DMA CRS Control and Status Register Mapping */ #define DMA_BUS_MODE … #define DMA_XMT_POLL_DEMAND … #define DMA_RCV_POLL_DEMAND … #define DMA_RCV_BASE_ADDR … #define DMA_TX_BASE_ADDR … #define DMA_STATUS … #define DMA_CONTROL … #define DMA_INTR_ENA … #define DMA_MISSED_FRAME_CTR … /* SW Reset */ #define DMA_BUS_MODE_SFT_RESET … /* Rx watchdog register */ #define DMA_RX_WATCHDOG … /* AXI Master Bus Mode */ #define DMA_AXI_BUS_MODE … #define DMA_AXI_EN_LPI … #define DMA_AXI_LPI_XIT_FRM … #define DMA_AXI_WR_OSR_LMT … #define DMA_AXI_WR_OSR_LMT_SHIFT … #define DMA_AXI_WR_OSR_LMT_MASK … #define DMA_AXI_RD_OSR_LMT … #define DMA_AXI_RD_OSR_LMT_SHIFT … #define DMA_AXI_RD_OSR_LMT_MASK … #define DMA_AXI_OSR_MAX … #define DMA_AXI_MAX_OSR_LIMIT … #define DMA_AXI_1KBBE … #define DMA_AXI_AAL … #define DMA_AXI_BLEN256 … #define DMA_AXI_BLEN128 … #define DMA_AXI_BLEN64 … #define DMA_AXI_BLEN32 … #define DMA_AXI_BLEN16 … #define DMA_AXI_BLEN8 … #define DMA_AXI_BLEN4 … #define DMA_BURST_LEN_DEFAULT … #define DMA_AXI_UNDEF … #define DMA_AXI_BURST_LEN_MASK … #define DMA_CUR_TX_BUF_ADDR … #define DMA_CUR_RX_BUF_ADDR … #define DMA_HW_FEATURE … /* DMA Control register defines */ #define DMA_CONTROL_ST … #define DMA_CONTROL_SR … /* DMA Normal interrupt */ #define DMA_INTR_ENA_NIE … #define DMA_INTR_ENA_TIE … #define DMA_INTR_ENA_TUE … #define DMA_INTR_ENA_RIE … #define DMA_INTR_ENA_ERE … #define DMA_INTR_NORMAL … /* DMA Abnormal interrupt */ #define DMA_INTR_ENA_AIE … #define DMA_INTR_ENA_FBE … #define DMA_INTR_ENA_ETE … #define DMA_INTR_ENA_RWE … #define DMA_INTR_ENA_RSE … #define DMA_INTR_ENA_RUE … #define DMA_INTR_ENA_UNE … #define DMA_INTR_ENA_OVE … #define DMA_INTR_ENA_TJE … #define DMA_INTR_ENA_TSE … #define DMA_INTR_ABNORMAL … /* DMA default interrupt mask */ #define DMA_INTR_DEFAULT_MASK … #define DMA_INTR_DEFAULT_RX … #define DMA_INTR_DEFAULT_TX … /* DMA Status register defines */ #define DMA_STATUS_GLPII … #define DMA_STATUS_GPI … #define DMA_STATUS_GMI … #define DMA_STATUS_GLI … #define DMA_STATUS_EB_MASK … #define DMA_STATUS_EB_TX_ABORT … #define DMA_STATUS_EB_RX_ABORT … #define DMA_STATUS_TS_MASK … #define DMA_STATUS_TS_SHIFT … #define DMA_STATUS_RS_MASK … #define DMA_STATUS_RS_SHIFT … #define DMA_STATUS_NIS … #define DMA_STATUS_AIS … #define DMA_STATUS_ERI … #define DMA_STATUS_FBI … #define DMA_STATUS_ETI … #define DMA_STATUS_RWT … #define DMA_STATUS_RPS … #define DMA_STATUS_RU … #define DMA_STATUS_RI … #define DMA_STATUS_UNF … #define DMA_STATUS_OVF … #define DMA_STATUS_TJT … #define DMA_STATUS_TU … #define DMA_STATUS_TPS … #define DMA_STATUS_TI … #define DMA_CONTROL_FTF … #define DMA_STATUS_MSK_COMMON … #define DMA_STATUS_MSK_RX … #define DMA_STATUS_MSK_TX … #define NUM_DWMAC100_DMA_REGS … #define NUM_DWMAC1000_DMA_REGS … #define NUM_DWMAC4_DMA_REGS … void dwmac_enable_dma_transmission(void __iomem *ioaddr); void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx); void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx); void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan); void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan); void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan); void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan); int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir); int dwmac_dma_reset(void __iomem *ioaddr); #endif /* __DWMAC_DMA_H__ */
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