/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* Copyright (C) 2007-2009 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __DWMAC1000_H__ #define __DWMAC1000_H__ #include <linux/phy.h> #include "common.h" #define GMAC_CONTROL … #define GMAC_FRAME_FILTER … #define GMAC_HASH_HIGH … #define GMAC_HASH_LOW … #define GMAC_MII_ADDR … #define GMAC_MII_DATA … #define GMAC_FLOW_CTRL … #define GMAC_VLAN_TAG … #define GMAC_DEBUG … #define GMAC_WAKEUP_FILTER … #define GMAC_INT_STATUS … #define GMAC_INT_STATUS_PMT … #define GMAC_INT_STATUS_MMCIS … #define GMAC_INT_STATUS_MMCRIS … #define GMAC_INT_STATUS_MMCTIS … #define GMAC_INT_STATUS_MMCCSUM … #define GMAC_INT_STATUS_TSTAMP … #define GMAC_INT_STATUS_LPIIS … /* interrupt mask register */ #define GMAC_INT_MASK … #define GMAC_INT_DISABLE_RGMII … #define GMAC_INT_DISABLE_PCSLINK … #define GMAC_INT_DISABLE_PCSAN … #define GMAC_INT_DISABLE_PMT … #define GMAC_INT_DISABLE_TIMESTAMP … #define GMAC_INT_DISABLE_PCS … #define GMAC_INT_DEFAULT_MASK … /* PMT Control and Status */ #define GMAC_PMT … enum power_event { … }; /* Energy Efficient Ethernet (EEE) * * LPI status, timer and control register offset */ #define LPI_CTRL_STATUS … #define LPI_TIMER_CTRL … /* LPI control and status defines */ #define LPI_CTRL_STATUS_LPITXA … #define LPI_CTRL_STATUS_PLSEN … #define LPI_CTRL_STATUS_PLS … #define LPI_CTRL_STATUS_LPIEN … #define LPI_CTRL_STATUS_RLPIST … #define LPI_CTRL_STATUS_TLPIST … #define LPI_CTRL_STATUS_RLPIEX … #define LPI_CTRL_STATUS_RLPIEN … #define LPI_CTRL_STATUS_TLPIEX … #define LPI_CTRL_STATUS_TLPIEN … /* GMAC HW ADDR regs */ #define GMAC_ADDR_HIGH(reg) … #define GMAC_ADDR_LOW(reg) … #define GMAC_MAX_PERFECT_ADDRESSES … #define GMAC_PCS_BASE … #define GMAC_RGSMIIIS … /* SGMII/RGMII status register */ #define GMAC_RGSMIIIS_LNKMODE … #define GMAC_RGSMIIIS_SPEED … #define GMAC_RGSMIIIS_SPEED_SHIFT … #define GMAC_RGSMIIIS_LNKSTS … #define GMAC_RGSMIIIS_JABTO … #define GMAC_RGSMIIIS_FALSECARDET … #define GMAC_RGSMIIIS_SMIDRXS … /* LNKMOD */ #define GMAC_RGSMIIIS_LNKMOD_MASK … /* LNKSPEED */ #define GMAC_RGSMIIIS_SPEED_125 … #define GMAC_RGSMIIIS_SPEED_25 … #define GMAC_RGSMIIIS_SPEED_2_5 … /* GMAC Configuration defines */ #define GMAC_CONTROL_2K … #define GMAC_CONTROL_TC … #define GMAC_CONTROL_WD … #define GMAC_CONTROL_JD … #define GMAC_CONTROL_BE … #define GMAC_CONTROL_JE … enum inter_frame_gap { … }; #define GMAC_CONTROL_DCRS … #define GMAC_CONTROL_PS … #define GMAC_CONTROL_FES … #define GMAC_CONTROL_DO … #define GMAC_CONTROL_LM … #define GMAC_CONTROL_DM … #define GMAC_CONTROL_IPC … #define GMAC_CONTROL_DR … #define GMAC_CONTROL_LUD … #define GMAC_CONTROL_ACS … #define GMAC_CONTROL_DC … #define GMAC_CONTROL_TE … #define GMAC_CONTROL_RE … #define GMAC_CORE_INIT … /* GMAC Frame Filter defines */ #define GMAC_FRAME_FILTER_PR … #define GMAC_FRAME_FILTER_HUC … #define GMAC_FRAME_FILTER_HMC … #define GMAC_FRAME_FILTER_DAIF … #define GMAC_FRAME_FILTER_PM … #define GMAC_FRAME_FILTER_DBF … #define GMAC_FRAME_FILTER_PCF … #define GMAC_FRAME_FILTER_SAIF … #define GMAC_FRAME_FILTER_SAF … #define GMAC_FRAME_FILTER_HPF … #define GMAC_FRAME_FILTER_RA … /* GMII ADDR defines */ #define GMAC_MII_ADDR_WRITE … #define GMAC_MII_ADDR_BUSY … /* GMAC FLOW CTRL defines */ #define GMAC_FLOW_CTRL_PT_MASK … #define GMAC_FLOW_CTRL_PT_SHIFT … #define GMAC_FLOW_CTRL_UP … #define GMAC_FLOW_CTRL_RFE … #define GMAC_FLOW_CTRL_TFE … #define GMAC_FLOW_CTRL_FCB_BPA … /* DEBUG Register defines */ /* MTL TxStatus FIFO */ #define GMAC_DEBUG_TXSTSFSTS … #define GMAC_DEBUG_TXFSTS … #define GMAC_DEBUG_TWCSTS … /* MTL Tx FIFO Read Controller Status */ #define GMAC_DEBUG_TRCSTS_MASK … #define GMAC_DEBUG_TRCSTS_SHIFT … #define GMAC_DEBUG_TRCSTS_IDLE … #define GMAC_DEBUG_TRCSTS_READ … #define GMAC_DEBUG_TRCSTS_TXW … #define GMAC_DEBUG_TRCSTS_WRITE … #define GMAC_DEBUG_TXPAUSED … /* MAC Transmit Frame Controller Status */ #define GMAC_DEBUG_TFCSTS_MASK … #define GMAC_DEBUG_TFCSTS_SHIFT … #define GMAC_DEBUG_TFCSTS_IDLE … #define GMAC_DEBUG_TFCSTS_WAIT … #define GMAC_DEBUG_TFCSTS_GEN_PAUSE … #define GMAC_DEBUG_TFCSTS_XFER … /* MAC GMII or MII Transmit Protocol Engine Status */ #define GMAC_DEBUG_TPESTS … #define GMAC_DEBUG_RXFSTS_MASK … #define GMAC_DEBUG_RXFSTS_SHIFT … #define GMAC_DEBUG_RXFSTS_EMPTY … #define GMAC_DEBUG_RXFSTS_BT … #define GMAC_DEBUG_RXFSTS_AT … #define GMAC_DEBUG_RXFSTS_FULL … #define GMAC_DEBUG_RRCSTS_MASK … #define GMAC_DEBUG_RRCSTS_SHIFT … #define GMAC_DEBUG_RRCSTS_IDLE … #define GMAC_DEBUG_RRCSTS_RDATA … #define GMAC_DEBUG_RRCSTS_RSTAT … #define GMAC_DEBUG_RRCSTS_FLUSH … #define GMAC_DEBUG_RWCSTS … /* MAC Receive Frame Controller FIFO Status */ #define GMAC_DEBUG_RFCFCSTS_MASK … #define GMAC_DEBUG_RFCFCSTS_SHIFT … /* MAC GMII or MII Receive Protocol Engine Status */ #define GMAC_DEBUG_RPESTS … /*--- DMA BLOCK defines ---*/ /* DMA Bus Mode register defines */ #define DMA_BUS_MODE_DA … #define DMA_BUS_MODE_DSL_MASK … #define DMA_BUS_MODE_DSL_SHIFT … /* Programmable burst length (passed thorugh platform)*/ #define DMA_BUS_MODE_PBL_MASK … #define DMA_BUS_MODE_PBL_SHIFT … #define DMA_BUS_MODE_ATDS … enum rx_tx_priority_ratio { … }; #define DMA_BUS_MODE_FB … #define DMA_BUS_MODE_MB … #define DMA_BUS_MODE_RPBL_MASK … #define DMA_BUS_MODE_RPBL_SHIFT … #define DMA_BUS_MODE_USP … #define DMA_BUS_MODE_MAXPBL … #define DMA_BUS_MODE_AAL … /* DMA CRS Control and Status Register Mapping */ #define DMA_HOST_TX_DESC … #define DMA_HOST_RX_DESC … /* DMA Bus Mode register defines */ #define DMA_BUS_PR_RATIO_MASK … #define DMA_BUS_PR_RATIO_SHIFT … #define DMA_BUS_FB … /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ /* Disable Drop TCP/IP csum error */ #define DMA_CONTROL_DT … #define DMA_CONTROL_RSF … #define DMA_CONTROL_DFF … /* Threshold for Activating the FC */ enum rfa { … }; /* Threshold for Deactivating the FC */ enum rfd { … }; #define DMA_CONTROL_TSF … enum ttc_control { … }; #define DMA_CONTROL_TC_TX_MASK … #define DMA_CONTROL_EFC … #define DMA_CONTROL_FEF … #define DMA_CONTROL_FUF … /* Receive flow control activation field * RFA field in DMA control register, bits 23,10:9 */ #define DMA_CONTROL_RFA_MASK … /* Receive flow control deactivation field * RFD field in DMA control register, bits 22,12:11 */ #define DMA_CONTROL_RFD_MASK … /* RFD and RFA fields are encoded as follows * * Bit Field * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled) * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled) * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled) * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled) * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled) * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled) * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled) * 1,11 - Reserved * * RFD should always be > RFA for a given FIFO size. RFD == RFA may work, * but packet throughput performance may not be as expected. * * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause * Description). * * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6), * is set to 0. This allows pause frames with a quanta of 0 to be sent * as an XOFF message to the link peer. */ #define RFA_FULL_MINUS_1K … #define RFA_FULL_MINUS_2K … #define RFA_FULL_MINUS_3K … #define RFA_FULL_MINUS_4K … #define RFA_FULL_MINUS_5K … #define RFA_FULL_MINUS_6K … #define RFA_FULL_MINUS_7K … #define RFD_FULL_MINUS_1K … #define RFD_FULL_MINUS_2K … #define RFD_FULL_MINUS_3K … #define RFD_FULL_MINUS_4K … #define RFD_FULL_MINUS_5K … #define RFD_FULL_MINUS_6K … #define RFD_FULL_MINUS_7K … enum rtc_control { … }; #define DMA_CONTROL_TC_RX_MASK … #define DMA_CONTROL_OSF … /* MMC registers offset */ #define GMAC_MMC_CTRL … #define GMAC_MMC_RX_INTR … #define GMAC_MMC_TX_INTR … #define GMAC_MMC_RX_CSUM_OFFLOAD … #define GMAC_EXTHASH_BASE … extern const struct stmmac_dma_ops dwmac1000_dma_ops; #endif /* __DWMAC1000_H__ */
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