/* SPDX-License-Identifier: GPL-2.0-only */ /******************************************************************************* MAC 10/100 Header File Copyright (C) 2007-2009 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #ifndef __DWMAC100_H__ #define __DWMAC100_H__ #include <linux/phy.h> #include "common.h" /*---------------------------------------------------------------------------- * MAC BLOCK defines *---------------------------------------------------------------------------*/ /* MAC CSR offset */ #define MAC_CONTROL … #define MAC_ADDR_HIGH … #define MAC_ADDR_LOW … #define MAC_HASH_HIGH … #define MAC_HASH_LOW … #define MAC_MII_ADDR … #define MAC_MII_DATA … #define MAC_FLOW_CTRL … #define MAC_VLAN1 … #define MAC_VLAN2 … /* MAC CTRL defines */ #define MAC_CONTROL_RA … #define MAC_CONTROL_BLE … #define MAC_CONTROL_HBD … #define MAC_CONTROL_PS … #define MAC_CONTROL_DRO … #define MAC_CONTROL_EXT_LOOPBACK … #define MAC_CONTROL_OM … #define MAC_CONTROL_F … #define MAC_CONTROL_PM … #define MAC_CONTROL_PR … #define MAC_CONTROL_IF … #define MAC_CONTROL_PB … #define MAC_CONTROL_HO … #define MAC_CONTROL_HP … #define MAC_CONTROL_LCC … #define MAC_CONTROL_DBF … #define MAC_CONTROL_DRTY … #define MAC_CONTROL_ASTP … #define MAC_CONTROL_BOLMT_10 … #define MAC_CONTROL_BOLMT_8 … #define MAC_CONTROL_BOLMT_4 … #define MAC_CONTROL_BOLMT_1 … #define MAC_CONTROL_DC … #define MAC_CONTROL_TE … #define MAC_CONTROL_RE … #define MAC_CORE_INIT … /* MAC FLOW CTRL defines */ #define MAC_FLOW_CTRL_PT_MASK … #define MAC_FLOW_CTRL_PT_SHIFT … #define MAC_FLOW_CTRL_PASS … #define MAC_FLOW_CTRL_ENABLE … #define MAC_FLOW_CTRL_PAUSE … /* MII ADDR defines */ #define MAC_MII_ADDR_WRITE … #define MAC_MII_ADDR_BUSY … /*---------------------------------------------------------------------------- * DMA BLOCK defines *---------------------------------------------------------------------------*/ /* DMA Bus Mode register defines */ #define DMA_BUS_MODE_DBO … #define DMA_BUS_MODE_BLE … #define DMA_BUS_MODE_PBL_MASK … #define DMA_BUS_MODE_PBL_SHIFT … #define DMA_BUS_MODE_DSL_MASK … #define DMA_BUS_MODE_DSL_SHIFT … #define DMA_BUS_MODE_BAR_BUS … #define DMA_BUS_MODE_DEFAULT … /* DMA Control register defines */ #define DMA_CONTROL_SF … /* Transmit Threshold Control */ enum ttc_control { … }; /* STMAC110 DMA Missed Frame Counter register defines */ #define DMA_MISSED_FRAME_OVE … #define DMA_MISSED_FRAME_OVE_CNTR … #define DMA_MISSED_FRAME_OVE_M … #define DMA_MISSED_FRAME_M_CNTR … extern const struct stmmac_dma_ops dwmac100_dma_ops; #endif /* __DWMAC100_H__ */
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