// SPDX-License-Identifier: GPL-2.0-only /******************************************************************************* DWMAC Management Counters Copyright (C) 2011 STMicroelectronics Ltd Author: Giuseppe Cavallaro <[email protected]> *******************************************************************************/ #include <linux/kernel.h> #include <linux/io.h> #include "hwif.h" #include "mmc.h" /* MAC Management Counters register offset */ #define MMC_CNTRL … #define MMC_RX_INTR … #define MMC_TX_INTR … #define MMC_RX_INTR_MASK … #define MMC_TX_INTR_MASK … #define MMC_DEFAULT_MASK … /* MMC TX counter registers */ /* Note: * _GB register stands for good and bad frames * _G is for good only. */ #define MMC_TX_OCTETCOUNT_GB … #define MMC_TX_FRAMECOUNT_GB … #define MMC_TX_BROADCASTFRAME_G … #define MMC_TX_MULTICASTFRAME_G … #define MMC_TX_64_OCTETS_GB … #define MMC_TX_65_TO_127_OCTETS_GB … #define MMC_TX_128_TO_255_OCTETS_GB … #define MMC_TX_256_TO_511_OCTETS_GB … #define MMC_TX_512_TO_1023_OCTETS_GB … #define MMC_TX_1024_TO_MAX_OCTETS_GB … #define MMC_TX_UNICAST_GB … #define MMC_TX_MULTICAST_GB … #define MMC_TX_BROADCAST_GB … #define MMC_TX_UNDERFLOW_ERROR … #define MMC_TX_SINGLECOL_G … #define MMC_TX_MULTICOL_G … #define MMC_TX_DEFERRED … #define MMC_TX_LATECOL … #define MMC_TX_EXESSCOL … #define MMC_TX_CARRIER_ERROR … #define MMC_TX_OCTETCOUNT_G … #define MMC_TX_FRAMECOUNT_G … #define MMC_TX_EXCESSDEF … #define MMC_TX_PAUSE_FRAME … #define MMC_TX_VLAN_FRAME_G … #define MMC_TX_OVERSIZE_G … /* MMC RX counter registers */ #define MMC_RX_FRAMECOUNT_GB … #define MMC_RX_OCTETCOUNT_GB … #define MMC_RX_OCTETCOUNT_G … #define MMC_RX_BROADCASTFRAME_G … #define MMC_RX_MULTICASTFRAME_G … #define MMC_RX_CRC_ERROR … #define MMC_RX_ALIGN_ERROR … #define MMC_RX_RUN_ERROR … #define MMC_RX_JABBER_ERROR … #define MMC_RX_UNDERSIZE_G … #define MMC_RX_OVERSIZE_G … #define MMC_RX_64_OCTETS_GB … #define MMC_RX_65_TO_127_OCTETS_GB … #define MMC_RX_128_TO_255_OCTETS_GB … #define MMC_RX_256_TO_511_OCTETS_GB … #define MMC_RX_512_TO_1023_OCTETS_GB … #define MMC_RX_1024_TO_MAX_OCTETS_GB … #define MMC_RX_UNICAST_G … #define MMC_RX_LENGTH_ERROR … #define MMC_RX_AUTOFRANGETYPE … #define MMC_RX_PAUSE_FRAMES … #define MMC_RX_FIFO_OVERFLOW … #define MMC_RX_VLAN_FRAMES_GB … #define MMC_RX_WATCHDOG_ERROR … #define MMC_RX_ERROR … #define MMC_TX_LPI_USEC … #define MMC_TX_LPI_TRAN … #define MMC_RX_LPI_USEC … #define MMC_RX_LPI_TRAN … /* IPC*/ #define MMC_RX_IPC_INTR_MASK … #define MMC_RX_IPC_INTR … /* IPv4*/ #define MMC_RX_IPV4_GD … #define MMC_RX_IPV4_HDERR … #define MMC_RX_IPV4_NOPAY … #define MMC_RX_IPV4_FRAG … #define MMC_RX_IPV4_UDSBL … #define MMC_RX_IPV4_GD_OCTETS … #define MMC_RX_IPV4_HDERR_OCTETS … #define MMC_RX_IPV4_NOPAY_OCTETS … #define MMC_RX_IPV4_FRAG_OCTETS … #define MMC_RX_IPV4_UDSBL_OCTETS … /* IPV6*/ #define MMC_RX_IPV6_GD_OCTETS … #define MMC_RX_IPV6_HDERR_OCTETS … #define MMC_RX_IPV6_NOPAY_OCTETS … #define MMC_RX_IPV6_GD … #define MMC_RX_IPV6_HDERR … #define MMC_RX_IPV6_NOPAY … /* Protocols*/ #define MMC_RX_UDP_GD … #define MMC_RX_UDP_ERR … #define MMC_RX_TCP_GD … #define MMC_RX_TCP_ERR … #define MMC_RX_ICMP_GD … #define MMC_RX_ICMP_ERR … #define MMC_RX_UDP_GD_OCTETS … #define MMC_RX_UDP_ERR_OCTETS … #define MMC_RX_TCP_GD_OCTETS … #define MMC_RX_TCP_ERR_OCTETS … #define MMC_RX_ICMP_GD_OCTETS … #define MMC_RX_ICMP_ERR_OCTETS … #define MMC_TX_FPE_FRAG … #define MMC_TX_HOLD_REQ … #define MMC_RX_PKT_ASSEMBLY_ERR … #define MMC_RX_PKT_SMD_ERR … #define MMC_RX_PKT_ASSEMBLY_OK … #define MMC_RX_FPE_FRAG … /* XGMAC MMC Registers */ #define MMC_XGMAC_TX_OCTET_GB … #define MMC_XGMAC_TX_PKT_GB … #define MMC_XGMAC_TX_BROAD_PKT_G … #define MMC_XGMAC_TX_MULTI_PKT_G … #define MMC_XGMAC_TX_64OCT_GB … #define MMC_XGMAC_TX_65OCT_GB … #define MMC_XGMAC_TX_128OCT_GB … #define MMC_XGMAC_TX_256OCT_GB … #define MMC_XGMAC_TX_512OCT_GB … #define MMC_XGMAC_TX_1024OCT_GB … #define MMC_XGMAC_TX_UNI_PKT_GB … #define MMC_XGMAC_TX_MULTI_PKT_GB … #define MMC_XGMAC_TX_BROAD_PKT_GB … #define MMC_XGMAC_TX_UNDER … #define MMC_XGMAC_TX_OCTET_G … #define MMC_XGMAC_TX_PKT_G … #define MMC_XGMAC_TX_PAUSE … #define MMC_XGMAC_TX_VLAN_PKT_G … #define MMC_XGMAC_TX_LPI_USEC … #define MMC_XGMAC_TX_LPI_TRAN … #define MMC_XGMAC_RX_PKT_GB … #define MMC_XGMAC_RX_OCTET_GB … #define MMC_XGMAC_RX_OCTET_G … #define MMC_XGMAC_RX_BROAD_PKT_G … #define MMC_XGMAC_RX_MULTI_PKT_G … #define MMC_XGMAC_RX_CRC_ERR … #define MMC_XGMAC_RX_RUNT_ERR … #define MMC_XGMAC_RX_JABBER_ERR … #define MMC_XGMAC_RX_UNDER … #define MMC_XGMAC_RX_OVER … #define MMC_XGMAC_RX_64OCT_GB … #define MMC_XGMAC_RX_65OCT_GB … #define MMC_XGMAC_RX_128OCT_GB … #define MMC_XGMAC_RX_256OCT_GB … #define MMC_XGMAC_RX_512OCT_GB … #define MMC_XGMAC_RX_1024OCT_GB … #define MMC_XGMAC_RX_UNI_PKT_G … #define MMC_XGMAC_RX_LENGTH_ERR … #define MMC_XGMAC_RX_RANGE … #define MMC_XGMAC_RX_PAUSE … #define MMC_XGMAC_RX_FIFOOVER_PKT … #define MMC_XGMAC_RX_VLAN_PKT_GB … #define MMC_XGMAC_RX_WATCHDOG_ERR … #define MMC_XGMAC_RX_LPI_USEC … #define MMC_XGMAC_RX_LPI_TRAN … #define MMC_XGMAC_RX_DISCARD_PKT_GB … #define MMC_XGMAC_RX_DISCARD_OCT_GB … #define MMC_XGMAC_RX_ALIGN_ERR_PKT … #define MMC_XGMAC_SGF_PASS_PKT … #define MMC_XGMAC_SGF_FAIL_PKT … #define MMC_XGMAC_TX_FPE_INTR_MASK … #define MMC_XGMAC_TX_FPE_FRAG … #define MMC_XGMAC_TX_HOLD_REQ … #define MMC_XGMAC_TX_GATE_OVERRUN … #define MMC_XGMAC_RX_FPE_INTR_MASK … #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR … #define MMC_XGMAC_RX_PKT_SMD_ERR … #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK … #define MMC_XGMAC_RX_FPE_FRAG … #define MMC_XGMAC_RX_IPC_INTR_MASK … #define MMC_XGMAC_RX_IPV4_GD … #define MMC_XGMAC_RX_IPV4_HDERR … #define MMC_XGMAC_RX_IPV4_NOPAY … #define MMC_XGMAC_RX_IPV4_FRAG … #define MMC_XGMAC_RX_IPV4_UDSBL … #define MMC_XGMAC_RX_IPV6_GD … #define MMC_XGMAC_RX_IPV6_HDERR … #define MMC_XGMAC_RX_IPV6_NOPAY … #define MMC_XGMAC_RX_UDP_GD … #define MMC_XGMAC_RX_UDP_ERR … #define MMC_XGMAC_RX_TCP_GD … #define MMC_XGMAC_RX_TCP_ERR … #define MMC_XGMAC_RX_ICMP_GD … #define MMC_XGMAC_RX_ICMP_ERR … #define MMC_XGMAC_RX_IPV4_GD_OCTETS … #define MMC_XGMAC_RX_IPV4_HDERR_OCTETS … #define MMC_XGMAC_RX_IPV4_NOPAY_OCTETS … #define MMC_XGMAC_RX_IPV4_FRAG_OCTETS … #define MMC_XGMAC_RX_IPV4_UDSBL_OCTETS … #define MMC_XGMAC_RX_IPV6_GD_OCTETS … #define MMC_XGMAC_RX_IPV6_HDERR_OCTETS … #define MMC_XGMAC_RX_IPV6_NOPAY_OCTETS … #define MMC_XGMAC_RX_UDP_GD_OCTETS … #define MMC_XGMAC_RX_UDP_ERR_OCTETS … #define MMC_XGMAC_RX_TCP_GD_OCTETS … #define MMC_XGMAC_RX_TCP_ERR_OCTETS … #define MMC_XGMAC_RX_ICMP_GD_OCTETS … #define MMC_XGMAC_RX_ICMP_ERR_OCTETS … static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) { … } /* To mask all interrupts.*/ static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr) { … } /* This reads the MAC core counters (if actaully supported). * by default the MMC core is programmed to reset each * counter after a read. So all the field of the mmc struct * have to be incremented. */ static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) { … } const struct stmmac_mmc_ops dwmac_mmc_ops = …; static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) { … } static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr) { … } static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest) { … } /* This reads the MAC core counters (if actaully supported). * by default the MMC core is programmed to reset each * counter after a read. So all the field of the mmc struct * have to be incremented. */ static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc) { … } const struct stmmac_mmc_ops dwxgmac_mmc_ops = …;
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