/* SPDX-License-Identifier: GPL-2.0-only */ /* * DWMAC4 Header file. * * Copyright (C) 2015 STMicroelectronics Ltd * * Author: Alexandre Torgue <[email protected]> */ #ifndef __DWMAC4_H__ #define __DWMAC4_H__ #include "common.h" /* MAC registers */ #define GMAC_CONFIG … #define GMAC_EXT_CONFIG … #define GMAC_PACKET_FILTER … #define GMAC_HASH_TAB(x) … #define GMAC_VLAN_TAG … #define GMAC_VLAN_TAG_DATA … #define GMAC_VLAN_HASH_TABLE … #define GMAC_RX_FLOW_CTRL … #define GMAC_VLAN_INCL … #define GMAC_QX_TX_FLOW_CTRL(x) … #define GMAC_TXQ_PRTY_MAP0 … #define GMAC_TXQ_PRTY_MAP1 … #define GMAC_RXQ_CTRL0 … #define GMAC_RXQ_CTRL1 … #define GMAC_RXQ_CTRL2 … #define GMAC_RXQ_CTRL3 … #define GMAC_INT_STATUS … #define GMAC_INT_EN … #define GMAC_1US_TIC_COUNTER … #define GMAC_PCS_BASE … #define GMAC_PHYIF_CONTROL_STATUS … #define GMAC_PMT … #define GMAC_DEBUG … #define GMAC_HW_FEATURE0 … #define GMAC_HW_FEATURE1 … #define GMAC_HW_FEATURE2 … #define GMAC_HW_FEATURE3 … #define GMAC_MDIO_ADDR … #define GMAC_MDIO_DATA … #define GMAC_GPIO_STATUS … #define GMAC_ARP_ADDR … #define GMAC_ADDR_HIGH(reg) … #define GMAC_ADDR_LOW(reg) … #define GMAC_L3L4_CTRL(reg) … #define GMAC_L4_ADDR(reg) … #define GMAC_L3_ADDR0(reg) … #define GMAC_L3_ADDR1(reg) … #define GMAC_TIMESTAMP_STATUS … /* RX Queues Routing */ #define GMAC_RXQCTRL_AVCPQ_MASK … #define GMAC_RXQCTRL_AVCPQ_SHIFT … #define GMAC_RXQCTRL_PTPQ_MASK … #define GMAC_RXQCTRL_PTPQ_SHIFT … #define GMAC_RXQCTRL_DCBCPQ_MASK … #define GMAC_RXQCTRL_DCBCPQ_SHIFT … #define GMAC_RXQCTRL_UPQ_MASK … #define GMAC_RXQCTRL_UPQ_SHIFT … #define GMAC_RXQCTRL_MCBCQ_MASK … #define GMAC_RXQCTRL_MCBCQ_SHIFT … #define GMAC_RXQCTRL_MCBCQEN … #define GMAC_RXQCTRL_MCBCQEN_SHIFT … #define GMAC_RXQCTRL_TACPQE … #define GMAC_RXQCTRL_TACPQE_SHIFT … #define GMAC_RXQCTRL_FPRQ … #define GMAC_RXQCTRL_FPRQ_SHIFT … /* MAC Packet Filtering */ #define GMAC_PACKET_FILTER_PR … #define GMAC_PACKET_FILTER_HMC … #define GMAC_PACKET_FILTER_PM … #define GMAC_PACKET_FILTER_PCF … #define GMAC_PACKET_FILTER_HPF … #define GMAC_PACKET_FILTER_VTFE … #define GMAC_PACKET_FILTER_IPFE … #define GMAC_PACKET_FILTER_RA … #define GMAC_MAX_PERFECT_ADDRESSES … /* MAC VLAN */ #define GMAC_VLAN_EDVLP … #define GMAC_VLAN_VTHM … #define GMAC_VLAN_DOVLTC … #define GMAC_VLAN_ESVL … #define GMAC_VLAN_ETV … #define GMAC_VLAN_VID … #define GMAC_VLAN_VLTI … #define GMAC_VLAN_CSVL … #define GMAC_VLAN_VLC … #define GMAC_VLAN_VLC_SHIFT … #define GMAC_VLAN_VLHT … /* MAC VLAN Tag */ #define GMAC_VLAN_TAG_VID … #define GMAC_VLAN_TAG_ETV … /* MAC VLAN Tag Control */ #define GMAC_VLAN_TAG_CTRL_OB … #define GMAC_VLAN_TAG_CTRL_CT … #define GMAC_VLAN_TAG_CTRL_OFS_MASK … #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT … #define GMAC_VLAN_TAG_CTRL_EVLS_MASK … #define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT … #define GMAC_VLAN_TAG_CTRL_EVLRXS … #define GMAC_VLAN_TAG_STRIP_NONE … #define GMAC_VLAN_TAG_STRIP_PASS … #define GMAC_VLAN_TAG_STRIP_FAIL … #define GMAC_VLAN_TAG_STRIP_ALL … /* MAC VLAN Tag Data/Filter */ #define GMAC_VLAN_TAG_DATA_VID … #define GMAC_VLAN_TAG_DATA_VEN … #define GMAC_VLAN_TAG_DATA_ETV … /* MAC RX Queue Enable */ #define GMAC_RX_QUEUE_CLEAR(queue) … #define GMAC_RX_AV_QUEUE_ENABLE(queue) … #define GMAC_RX_DCB_QUEUE_ENABLE(queue) … /* MAC Flow Control RX */ #define GMAC_RX_FLOW_CTRL_RFE … /* RX Queues Priorities */ #define GMAC_RXQCTRL_PSRQX_MASK(x) … #define GMAC_RXQCTRL_PSRQX_SHIFT(x) … /* TX Queues Priorities */ #define GMAC_TXQCTRL_PSTQX_MASK(x) … #define GMAC_TXQCTRL_PSTQX_SHIFT(x) … /* MAC Flow Control TX */ #define GMAC_TX_FLOW_CTRL_TFE … #define GMAC_TX_FLOW_CTRL_PT_SHIFT … /* MAC Interrupt bitmap*/ #define GMAC_INT_RGSMIIS … #define GMAC_INT_PCS_LINK … #define GMAC_INT_PCS_ANE … #define GMAC_INT_PCS_PHYIS … #define GMAC_INT_PMT_EN … #define GMAC_INT_LPI_EN … #define GMAC_INT_TSIE … #define GMAC_PCS_IRQ_DEFAULT … #define GMAC_INT_DEFAULT_ENABLE … enum dwmac4_irq_status { … }; /* MAC PMT bitmap */ enum power_event { … }; /* Energy Efficient Ethernet (EEE) for GMAC4 * * LPI status, timer and control register offset */ #define GMAC4_LPI_CTRL_STATUS … #define GMAC4_LPI_TIMER_CTRL … #define GMAC4_LPI_ENTRY_TIMER … #define GMAC4_MAC_ONEUS_TIC_COUNTER … /* LPI control and status defines */ #define GMAC4_LPI_CTRL_STATUS_LPITCSE … #define GMAC4_LPI_CTRL_STATUS_LPIATE … #define GMAC4_LPI_CTRL_STATUS_LPITXA … #define GMAC4_LPI_CTRL_STATUS_PLS … #define GMAC4_LPI_CTRL_STATUS_LPIEN … #define GMAC4_LPI_CTRL_STATUS_RLPIEX … #define GMAC4_LPI_CTRL_STATUS_RLPIEN … #define GMAC4_LPI_CTRL_STATUS_TLPIEX … #define GMAC4_LPI_CTRL_STATUS_TLPIEN … /* MAC Debug bitmap */ #define GMAC_DEBUG_TFCSTS_MASK … #define GMAC_DEBUG_TFCSTS_SHIFT … #define GMAC_DEBUG_TFCSTS_IDLE … #define GMAC_DEBUG_TFCSTS_WAIT … #define GMAC_DEBUG_TFCSTS_GEN_PAUSE … #define GMAC_DEBUG_TFCSTS_XFER … #define GMAC_DEBUG_TPESTS … #define GMAC_DEBUG_RFCFCSTS_MASK … #define GMAC_DEBUG_RFCFCSTS_SHIFT … #define GMAC_DEBUG_RPESTS … /* MAC config */ #define GMAC_CONFIG_ARPEN … #define GMAC_CONFIG_SARC … #define GMAC_CONFIG_SARC_SHIFT … #define GMAC_CONFIG_IPC … #define GMAC_CONFIG_IPG … #define GMAC_CONFIG_IPG_SHIFT … #define GMAC_CONFIG_2K … #define GMAC_CONFIG_ACS … #define GMAC_CONFIG_BE … #define GMAC_CONFIG_JD … #define GMAC_CONFIG_JE … #define GMAC_CONFIG_PS … #define GMAC_CONFIG_FES … #define GMAC_CONFIG_FES_SHIFT … #define GMAC_CONFIG_DM … #define GMAC_CONFIG_LM … #define GMAC_CONFIG_DCRS … #define GMAC_CONFIG_TE … #define GMAC_CONFIG_RE … /* MAC extended config */ #define GMAC_CONFIG_EIPG … #define GMAC_CONFIG_EIPG_SHIFT … #define GMAC_CONFIG_EIPG_EN … #define GMAC_CONFIG_HDSMS … #define GMAC_CONFIG_HDSMS_SHIFT … #define GMAC_CONFIG_HDSMS_256 … /* MAC HW features0 bitmap */ #define GMAC_HW_FEAT_SAVLANINS … #define GMAC_HW_FEAT_ADDMAC … #define GMAC_HW_FEAT_RXCOESEL … #define GMAC_HW_FEAT_TXCOSEL … #define GMAC_HW_FEAT_EEESEL … #define GMAC_HW_FEAT_TSSEL … #define GMAC_HW_FEAT_ARPOFFSEL … #define GMAC_HW_FEAT_MMCSEL … #define GMAC_HW_FEAT_MGKSEL … #define GMAC_HW_FEAT_RWKSEL … #define GMAC_HW_FEAT_SMASEL … #define GMAC_HW_FEAT_VLHASH … #define GMAC_HW_FEAT_PCSSEL … #define GMAC_HW_FEAT_HDSEL … #define GMAC_HW_FEAT_GMIISEL … #define GMAC_HW_FEAT_MIISEL … /* MAC HW features1 bitmap */ #define GMAC_HW_FEAT_L3L4FNUM … #define GMAC_HW_HASH_TB_SZ … #define GMAC_HW_FEAT_AVSEL … #define GMAC_HW_TSOEN … #define GMAC_HW_FEAT_SPHEN … #define GMAC_HW_ADDR64 … #define GMAC_HW_TXFIFOSIZE … #define GMAC_HW_RXFIFOSIZE … /* MAC HW features2 bitmap */ #define GMAC_HW_FEAT_AUXSNAPNUM … #define GMAC_HW_FEAT_PPSOUTNUM … #define GMAC_HW_FEAT_TXCHCNT … #define GMAC_HW_FEAT_RXCHCNT … #define GMAC_HW_FEAT_TXQCNT … #define GMAC_HW_FEAT_RXQCNT … /* MAC HW features3 bitmap */ #define GMAC_HW_FEAT_ASP … #define GMAC_HW_FEAT_TBSSEL … #define GMAC_HW_FEAT_FPESEL … #define GMAC_HW_FEAT_ESTWID … #define GMAC_HW_FEAT_ESTDEP … #define GMAC_HW_FEAT_ESTSEL … #define GMAC_HW_FEAT_FRPES … #define GMAC_HW_FEAT_FRPBS … #define GMAC_HW_FEAT_FRPSEL … #define GMAC_HW_FEAT_DVLAN … #define GMAC_HW_FEAT_NRVF … /* GMAC GPIO Status reg */ #define GMAC_GPO0 … #define GMAC_GPO1 … #define GMAC_GPO2 … #define GMAC_GPO3 … /* MAC HW ADDR regs */ #define GMAC_HI_DCS … #define GMAC_HI_DCS_SHIFT … #define GMAC_HI_REG_AE … /* L3/L4 Filters regs */ #define GMAC_L4DPIM0 … #define GMAC_L4DPM0 … #define GMAC_L4SPIM0 … #define GMAC_L4SPM0 … #define GMAC_L4PEN0 … #define GMAC_L3DAIM0 … #define GMAC_L3DAM0 … #define GMAC_L3SAIM0 … #define GMAC_L3SAM0 … #define GMAC_L3PEN0 … #define GMAC_L4DP0 … #define GMAC_L4DP0_SHIFT … #define GMAC_L4SP0 … /* MAC Timestamp Status */ #define GMAC_TIMESTAMP_AUXTSTRIG … #define GMAC_TIMESTAMP_ATSNS_MASK … #define GMAC_TIMESTAMP_ATSNS_SHIFT … /* MTL registers */ #define MTL_OPERATION_MODE … #define MTL_FRPE … #define MTL_OPERATION_SCHALG_MASK … #define MTL_OPERATION_SCHALG_WRR … #define MTL_OPERATION_SCHALG_WFQ … #define MTL_OPERATION_SCHALG_DWRR … #define MTL_OPERATION_SCHALG_SP … #define MTL_OPERATION_RAA … #define MTL_OPERATION_RAA_SP … #define MTL_OPERATION_RAA_WSP … #define MTL_INT_STATUS … #define MTL_INT_QX(x) … #define MTL_RXQ_DMA_MAP0 … #define MTL_RXQ_DMA_MAP1 … #define MTL_RXQ_DMA_QXMDMACH_MASK(x) … #define MTL_RXQ_DMA_QXMDMACH(chan, q) … #define MTL_CHAN_BASE_ADDR … #define MTL_CHAN_BASE_OFFSET … static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_CHAN_TX_OP_MODE(addrs, x) … #define MTL_CHAN_TX_DEBUG(addrs, x) … #define MTL_CHAN_INT_CTRL(addrs, x) … #define MTL_CHAN_RX_OP_MODE(addrs, x) … #define MTL_CHAN_RX_DEBUG(addrs, x) … #define MTL_OP_MODE_RSF … #define MTL_OP_MODE_TXQEN_MASK … #define MTL_OP_MODE_TXQEN_AV … #define MTL_OP_MODE_TXQEN … #define MTL_OP_MODE_TSF … #define MTL_OP_MODE_TQS_MASK … #define MTL_OP_MODE_TQS_SHIFT … #define MTL_OP_MODE_TTC_MASK … #define MTL_OP_MODE_TTC_SHIFT … #define MTL_OP_MODE_TTC_32 … #define MTL_OP_MODE_TTC_64 … #define MTL_OP_MODE_TTC_96 … #define MTL_OP_MODE_TTC_128 … #define MTL_OP_MODE_TTC_192 … #define MTL_OP_MODE_TTC_256 … #define MTL_OP_MODE_TTC_384 … #define MTL_OP_MODE_TTC_512 … #define MTL_OP_MODE_RQS_MASK … #define MTL_OP_MODE_RQS_SHIFT … #define MTL_OP_MODE_RFD_MASK … #define MTL_OP_MODE_RFD_SHIFT … #define MTL_OP_MODE_RFA_MASK … #define MTL_OP_MODE_RFA_SHIFT … #define MTL_OP_MODE_EHFC … #define MTL_OP_MODE_RTC_MASK … #define MTL_OP_MODE_RTC_SHIFT … #define MTL_OP_MODE_RTC_32 … #define MTL_OP_MODE_RTC_64 … #define MTL_OP_MODE_RTC_96 … #define MTL_OP_MODE_RTC_128 … /* MTL ETS Control register */ #define MTL_ETS_CTRL_BASE_ADDR … #define MTL_ETS_CTRL_BASE_OFFSET … static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_ETS_CTRL_CC … #define MTL_ETS_CTRL_AVALG … /* MTL Queue Quantum Weight */ #define MTL_TXQ_WEIGHT_BASE_ADDR … #define MTL_TXQ_WEIGHT_BASE_OFFSET … static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_TXQ_WEIGHT_ISCQW_MASK … /* MTL sendSlopeCredit register */ #define MTL_SEND_SLP_CRED_BASE_ADDR … #define MTL_SEND_SLP_CRED_OFFSET … static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_SEND_SLP_CRED_SSC_MASK … /* MTL hiCredit register */ #define MTL_HIGH_CRED_BASE_ADDR … #define MTL_HIGH_CRED_OFFSET … static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_HIGH_CRED_HC_MASK … /* MTL loCredit register */ #define MTL_LOW_CRED_BASE_ADDR … #define MTL_LOW_CRED_OFFSET … static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs, const u32 x) { … } #define MTL_HIGH_CRED_LC_MASK … /* MTL debug */ #define MTL_DEBUG_TXSTSFSTS … #define MTL_DEBUG_TXFSTS … #define MTL_DEBUG_TWCSTS … /* MTL debug: Tx FIFO Read Controller Status */ #define MTL_DEBUG_TRCSTS_MASK … #define MTL_DEBUG_TRCSTS_SHIFT … #define MTL_DEBUG_TRCSTS_IDLE … #define MTL_DEBUG_TRCSTS_READ … #define MTL_DEBUG_TRCSTS_TXW … #define MTL_DEBUG_TRCSTS_WRITE … #define MTL_DEBUG_TXPAUSED … /* MAC debug: GMII or MII Transmit Protocol Engine Status */ #define MTL_DEBUG_RXFSTS_MASK … #define MTL_DEBUG_RXFSTS_SHIFT … #define MTL_DEBUG_RXFSTS_EMPTY … #define MTL_DEBUG_RXFSTS_BT … #define MTL_DEBUG_RXFSTS_AT … #define MTL_DEBUG_RXFSTS_FULL … #define MTL_DEBUG_RRCSTS_MASK … #define MTL_DEBUG_RRCSTS_SHIFT … #define MTL_DEBUG_RRCSTS_IDLE … #define MTL_DEBUG_RRCSTS_RDATA … #define MTL_DEBUG_RRCSTS_RSTAT … #define MTL_DEBUG_RRCSTS_FLUSH … #define MTL_DEBUG_RWCSTS … /* MTL interrupt */ #define MTL_RX_OVERFLOW_INT_EN … #define MTL_RX_OVERFLOW_INT … /* Default operating mode of the MAC */ #define GMAC_CORE_INIT … /* To dump the core regs excluding the Address Registers */ #define GMAC_REG_NUM … /* MTL debug */ #define MTL_DEBUG_TXSTSFSTS … #define MTL_DEBUG_TXFSTS … #define MTL_DEBUG_TWCSTS … /* MTL debug: Tx FIFO Read Controller Status */ #define MTL_DEBUG_TRCSTS_MASK … #define MTL_DEBUG_TRCSTS_SHIFT … #define MTL_DEBUG_TRCSTS_IDLE … #define MTL_DEBUG_TRCSTS_READ … #define MTL_DEBUG_TRCSTS_TXW … #define MTL_DEBUG_TRCSTS_WRITE … #define MTL_DEBUG_TXPAUSED … /* MAC debug: GMII or MII Transmit Protocol Engine Status */ #define MTL_DEBUG_RXFSTS_MASK … #define MTL_DEBUG_RXFSTS_SHIFT … #define MTL_DEBUG_RXFSTS_EMPTY … #define MTL_DEBUG_RXFSTS_BT … #define MTL_DEBUG_RXFSTS_AT … #define MTL_DEBUG_RXFSTS_FULL … #define MTL_DEBUG_RRCSTS_MASK … #define MTL_DEBUG_RRCSTS_SHIFT … #define MTL_DEBUG_RRCSTS_IDLE … #define MTL_DEBUG_RRCSTS_RDATA … #define MTL_DEBUG_RRCSTS_RSTAT … #define MTL_DEBUG_RRCSTS_FLUSH … #define MTL_DEBUG_RWCSTS … /* SGMII/RGMII status register */ #define GMAC_PHYIF_CTRLSTATUS_TC … #define GMAC_PHYIF_CTRLSTATUS_LUD … #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS … #define GMAC_PHYIF_CTRLSTATUS_LNKMOD … #define GMAC_PHYIF_CTRLSTATUS_SPEED … #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT … #define GMAC_PHYIF_CTRLSTATUS_LNKSTS … #define GMAC_PHYIF_CTRLSTATUS_JABTO … #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET … /* LNKSPEED */ #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 … #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 … #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 … extern const struct stmmac_dma_ops dwmac4_dma_ops; extern const struct stmmac_dma_ops dwmac410_dma_ops; #endif /* __DWMAC4_H__ */
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