dwmac4_dma.h | Explore in Territory

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DWMAC4 DMA Header file.
 *
 * Copyright (C) 2007-2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <[email protected]>
 */

#ifndef __DWMAC4_DMA_H__
#define __DWMAC4_DMA_H__

/* Define the max channel number used for tx (also rx).
 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
 */
#define DMA_CHANNEL_NB_MAX …

#define DMA_BUS_MODE …
#define DMA_SYS_BUS_MODE …
#define DMA_STATUS …
#define DMA_DEBUG_STATUS_0 …
#define DMA_DEBUG_STATUS_1 …
#define DMA_DEBUG_STATUS_2 …
#define DMA_AXI_BUS_MODE …
#define DMA_TBS_CTRL …

/* DMA Bus Mode bitmap */
#define DMA_BUS_MODE_DCHE …
#define DMA_BUS_MODE_INTM_MASK …
#define DMA_BUS_MODE_INTM_SHIFT …
#define DMA_BUS_MODE_INTM_MODE1 …
#define DMA_BUS_MODE_SFT_RESET …

/* DMA SYS Bus Mode bitmap */
#define DMA_BUS_MODE_SPH …
#define DMA_BUS_MODE_PBL …
#define DMA_BUS_MODE_PBL_SHIFT …
#define DMA_BUS_MODE_RPBL_SHIFT …
#define DMA_BUS_MODE_MB …
#define DMA_BUS_MODE_FB …

/* DMA Interrupt top status */
#define DMA_STATUS_MAC …
#define DMA_STATUS_MTL …
#define DMA_STATUS_CHAN7 …
#define DMA_STATUS_CHAN6 …
#define DMA_STATUS_CHAN5 …
#define DMA_STATUS_CHAN4 …
#define DMA_STATUS_CHAN3 …
#define DMA_STATUS_CHAN2 …
#define DMA_STATUS_CHAN1 …
#define DMA_STATUS_CHAN0 …

/* DMA debug status bitmap */
#define DMA_DEBUG_STATUS_TS_MASK …
#define DMA_DEBUG_STATUS_RS_MASK …

/* DMA AXI bitmap */
#define DMA_AXI_EN_LPI …
#define DMA_AXI_LPI_XIT_FRM …
#define DMA_AXI_WR_OSR_LMT …
#define DMA_AXI_WR_OSR_LMT_SHIFT …
#define DMA_AXI_RD_OSR_LMT …
#define DMA_AXI_RD_OSR_LMT_SHIFT …

#define DMA_AXI_OSR_MAX …
#define DMA_AXI_MAX_OSR_LIMIT …

#define DMA_SYS_BUS_MB …
#define DMA_AXI_1KBBE …
#define DMA_SYS_BUS_AAL …
#define DMA_SYS_BUS_EAME …
#define DMA_AXI_BLEN256 …
#define DMA_AXI_BLEN128 …
#define DMA_AXI_BLEN64 …
#define DMA_AXI_BLEN32 …
#define DMA_AXI_BLEN16 …
#define DMA_AXI_BLEN8 …
#define DMA_AXI_BLEN4 …
#define DMA_SYS_BUS_FB …

#define DMA_BURST_LEN_DEFAULT …

#define DMA_AXI_BURST_LEN_MASK …

/* DMA TBS Control */
#define DMA_TBS_FTOS …
#define DMA_TBS_FTOV …
#define DMA_TBS_DEF_FTOS …

/* Following DMA defines are channel-oriented */
#define DMA_CHAN_BASE_ADDR …
#define DMA_CHAN_BASE_OFFSET …

static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
				      const u32 x)
{ … }

#define DMA_CHAN_REG_NUMBER …

#define DMA_CHAN_CONTROL(addrs, x) …
#define DMA_CHAN_TX_CONTROL(addrs, x) …
#define DMA_CHAN_RX_CONTROL(addrs, x) …
#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) …
#define DMA_CHAN_TX_BASE_ADDR(addrs, x) …
#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) …
#define DMA_CHAN_RX_BASE_ADDR(addrs, x) …
#define DMA_CHAN_TX_END_ADDR(addrs, x) …
#define DMA_CHAN_RX_END_ADDR(addrs, x) …
#define DMA_CHAN_TX_RING_LEN(addrs, x) …
#define DMA_CHAN_RX_RING_LEN(addrs, x) …
#define DMA_CHAN_INTR_ENA(addrs, x) …
#define DMA_CHAN_RX_WATCHDOG(addrs, x) …
#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) …
#define DMA_CHAN_CUR_TX_DESC(addrs, x) …
#define DMA_CHAN_CUR_RX_DESC(addrs, x) …
#define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) …
#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) …
#define DMA_CHAN_STATUS(addrs, x) …

/* DMA Control X */
#define DMA_CONTROL_SPH …
#define DMA_CONTROL_MSS_MASK …

/* DMA Tx Channel X Control register defines */
#define DMA_CONTROL_EDSE …
#define DMA_CONTROL_TSE …
#define DMA_CONTROL_OSP …
#define DMA_CONTROL_ST …

/* DMA Rx Channel X Control register defines */
#define DMA_CONTROL_SR …
#define DMA_RBSZ_MASK …
#define DMA_RBSZ_SHIFT …

/* Interrupt status per channel */
#define DMA_CHAN_STATUS_REB …
#define DMA_CHAN_STATUS_REB_SHIFT …
#define DMA_CHAN_STATUS_TEB …
#define DMA_CHAN_STATUS_TEB_SHIFT …
#define DMA_CHAN_STATUS_NIS …
#define DMA_CHAN_STATUS_AIS …
#define DMA_CHAN_STATUS_CDE …
#define DMA_CHAN_STATUS_FBE …
#define DMA_CHAN_STATUS_ERI …
#define DMA_CHAN_STATUS_ETI …
#define DMA_CHAN_STATUS_RWT …
#define DMA_CHAN_STATUS_RPS …
#define DMA_CHAN_STATUS_RBU …
#define DMA_CHAN_STATUS_RI …
#define DMA_CHAN_STATUS_TBU …
#define DMA_CHAN_STATUS_TPS …
#define DMA_CHAN_STATUS_TI …

#define DMA_CHAN_STATUS_MSK_COMMON …

#define DMA_CHAN_STATUS_MSK_RX …

#define DMA_CHAN_STATUS_MSK_TX …

/* Interrupt enable bits per channel */
#define DMA_CHAN_INTR_ENA_NIE …
#define DMA_CHAN_INTR_ENA_AIE …
#define DMA_CHAN_INTR_ENA_NIE_4_10 …
#define DMA_CHAN_INTR_ENA_AIE_4_10 …
#define DMA_CHAN_INTR_ENA_CDE …
#define DMA_CHAN_INTR_ENA_FBE …
#define DMA_CHAN_INTR_ENA_ERE …
#define DMA_CHAN_INTR_ENA_ETE …
#define DMA_CHAN_INTR_ENA_RWE …
#define DMA_CHAN_INTR_ENA_RSE …
#define DMA_CHAN_INTR_ENA_RBUE …
#define DMA_CHAN_INTR_ENA_RIE …
#define DMA_CHAN_INTR_ENA_TBUE …
#define DMA_CHAN_INTR_ENA_TSE …
#define DMA_CHAN_INTR_ENA_TIE …

#define DMA_CHAN_INTR_NORMAL …

#define DMA_CHAN_INTR_ABNORMAL …
/* DMA default interrupt mask for 4.00 */
#define DMA_CHAN_INTR_DEFAULT_MASK …
#define DMA_CHAN_INTR_DEFAULT_RX …
#define DMA_CHAN_INTR_DEFAULT_TX …

#define DMA_CHAN_INTR_NORMAL_4_10 …

#define DMA_CHAN_INTR_ABNORMAL_4_10 …
/* DMA default interrupt mask for 4.10a */
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 …
#define DMA_CHAN_INTR_DEFAULT_RX_4_10 …
#define DMA_CHAN_INTR_DEFAULT_TX_4_10 …

/* channel 0 specific fields */
#define DMA_CHAN0_DBG_STAT_TPS …
#define DMA_CHAN0_DBG_STAT_TPS_SHIFT …
#define DMA_CHAN0_DBG_STAT_RPS …
#define DMA_CHAN0_DBG_STAT_RPS_SHIFT …

int dwmac4_dma_reset(void __iomem *ioaddr);
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			   u32 chan, bool rx, bool tx);
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			     u32 chan, bool rx, bool tx);
void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 chan, bool rx, bool tx);
void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			      u32 chan, bool rx, bool tx);
void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
			 u32 chan);
void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
			u32 chan);
void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
			 u32 chan);
void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
			u32 chan);
int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
			 struct stmmac_extra_stats *x, u32 chan, u32 dir);
void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 len, u32 chan);
void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 len, u32 chan);
void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 tail_ptr, u32 chan);
void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 tail_ptr, u32 chan);

#endif /* __DWMAC4_DMA_H__ */
linux/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
