/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header File to describe the DMA descriptors and related definitions specific * for DesignWare databook 4.xx. * * Copyright (C) 2015 STMicroelectronics Ltd * * Author: Alexandre Torgue <[email protected]> */ #ifndef __DWMAC4_DESCS_H__ #define __DWMAC4_DESCS_H__ #include <linux/bitops.h> /* Normal transmit descriptor defines (without split feature) */ /* TDES2 (read format) */ #define TDES2_BUFFER1_SIZE_MASK … #define TDES2_VLAN_TAG_MASK … #define TDES2_VLAN_TAG_SHIFT … #define TDES2_BUFFER2_SIZE_MASK … #define TDES2_BUFFER2_SIZE_MASK_SHIFT … #define TDES3_IVTIR_MASK … #define TDES3_IVTIR_SHIFT … #define TDES3_IVLTV … #define TDES2_TIMESTAMP_ENABLE … #define TDES2_IVT_MASK … #define TDES2_IVT_SHIFT … #define TDES2_INTERRUPT_ON_COMPLETION … /* TDES3 (read format) */ #define TDES3_PACKET_SIZE_MASK … #define TDES3_VLAN_TAG … #define TDES3_VLTV … #define TDES3_CHECKSUM_INSERTION_MASK … #define TDES3_CHECKSUM_INSERTION_SHIFT … #define TDES3_TCP_PKT_PAYLOAD_MASK … #define TDES3_TCP_SEGMENTATION_ENABLE … #define TDES3_HDR_LEN_SHIFT … #define TDES3_SLOT_NUMBER_MASK … #define TDES3_SA_INSERT_CTRL_MASK … #define TDES3_SA_INSERT_CTRL_SHIFT … #define TDES3_CRC_PAD_CTRL_MASK … /* TDES3 (write back format) */ #define TDES3_IP_HDR_ERROR … #define TDES3_DEFERRED … #define TDES3_UNDERFLOW_ERROR … #define TDES3_EXCESSIVE_DEFERRAL … #define TDES3_COLLISION_COUNT_MASK … #define TDES3_COLLISION_COUNT_SHIFT … #define TDES3_EXCESSIVE_COLLISION … #define TDES3_LATE_COLLISION … #define TDES3_NO_CARRIER … #define TDES3_LOSS_CARRIER … #define TDES3_PAYLOAD_ERROR … #define TDES3_PACKET_FLUSHED … #define TDES3_JABBER_TIMEOUT … #define TDES3_ERROR_SUMMARY … #define TDES3_TIMESTAMP_STATUS … #define TDES3_TIMESTAMP_STATUS_SHIFT … /* TDES3 context */ #define TDES3_CTXT_TCMSSV … /* TDES3 Common */ #define TDES3_RS1V … #define TDES3_RS1V_SHIFT … #define TDES3_LAST_DESCRIPTOR … #define TDES3_LAST_DESCRIPTOR_SHIFT … #define TDES3_FIRST_DESCRIPTOR … #define TDES3_CONTEXT_TYPE … #define TDES3_CONTEXT_TYPE_SHIFT … /* TDES4 */ #define TDES4_LTV … #define TDES4_LT … /* TDES5 */ #define TDES5_LT … /* TDS3 use for both format (read and write back) */ #define TDES3_OWN … #define TDES3_OWN_SHIFT … /* Normal receive descriptor defines (without split feature) */ /* RDES0 (write back format) */ #define RDES0_VLAN_TAG_MASK … /* RDES1 (write back format) */ #define RDES1_IP_PAYLOAD_TYPE_MASK … #define RDES1_IP_HDR_ERROR … #define RDES1_IPV4_HEADER … #define RDES1_IPV6_HEADER … #define RDES1_IP_CSUM_BYPASSED … #define RDES1_IP_CSUM_ERROR … #define RDES1_PTP_MSG_TYPE_MASK … #define RDES1_PTP_PACKET_TYPE … #define RDES1_PTP_VER … #define RDES1_TIMESTAMP_AVAILABLE … #define RDES1_TIMESTAMP_AVAILABLE_SHIFT … #define RDES1_TIMESTAMP_DROPPED … #define RDES1_IP_TYPE1_CSUM_MASK … /* RDES2 (write back format) */ #define RDES2_L3_L4_HEADER_SIZE_MASK … #define RDES2_VLAN_FILTER_STATUS … #define RDES2_SA_FILTER_FAIL … #define RDES2_DA_FILTER_FAIL … #define RDES2_HASH_FILTER_STATUS … #define RDES2_MAC_ADDR_MATCH_MASK … #define RDES2_HASH_VALUE_MATCH_MASK … #define RDES2_L3_FILTER_MATCH … #define RDES2_L4_FILTER_MATCH … #define RDES2_L3_L4_FILT_NB_MATCH_MASK … #define RDES2_L3_L4_FILT_NB_MATCH_SHIFT … #define RDES2_HL … /* RDES3 (write back format) */ #define RDES3_PACKET_SIZE_MASK … #define RDES3_ERROR_SUMMARY … #define RDES3_PACKET_LEN_TYPE_MASK … #define RDES3_DRIBBLE_ERROR … #define RDES3_RECEIVE_ERROR … #define RDES3_OVERFLOW_ERROR … #define RDES3_RECEIVE_WATCHDOG … #define RDES3_GIANT_PACKET … #define RDES3_CRC_ERROR … #define RDES3_RDES0_VALID … #define RDES3_RDES1_VALID … #define RDES3_RDES2_VALID … #define RDES3_LAST_DESCRIPTOR … #define RDES3_FIRST_DESCRIPTOR … #define RDES3_CONTEXT_DESCRIPTOR … #define RDES3_CONTEXT_DESCRIPTOR_SHIFT … /* RDES3 (read format) */ #define RDES3_BUFFER1_VALID_ADDR … #define RDES3_BUFFER2_VALID_ADDR … #define RDES3_INT_ON_COMPLETION_EN … /* TDS3 use for both format (read and write back) */ #define RDES3_OWN … #endif /* __DWMAC4_DESCS_H__ */
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