// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018-19, Linaro Limited #include <linux/module.h> #include <linux/of.h> #include <linux/of_net.h> #include <linux/platform_device.h> #include <linux/phy.h> #include <linux/phy/phy.h> #include "stmmac.h" #include "stmmac_platform.h" #define RGMII_IO_MACRO_CONFIG … #define SDCC_HC_REG_DLL_CONFIG … #define SDCC_TEST_CTL … #define SDCC_HC_REG_DDR_CONFIG … #define SDCC_HC_REG_DLL_CONFIG2 … #define SDC4_STATUS … #define SDCC_USR_CTL … #define RGMII_IO_MACRO_CONFIG2 … #define RGMII_IO_MACRO_DEBUG1 … #define EMAC_SYSTEM_LOW_POWER_DEBUG … #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 … /* RGMII_IO_MACRO_CONFIG fields */ #define RGMII_CONFIG_FUNC_CLK_EN … #define RGMII_CONFIG_POS_NEG_DATA_SEL … #define RGMII_CONFIG_GPIO_CFG_RX_INT … #define RGMII_CONFIG_GPIO_CFG_TX_INT … #define RGMII_CONFIG_MAX_SPD_PRG_9 … #define RGMII_CONFIG_MAX_SPD_PRG_2 … #define RGMII_CONFIG_INTF_SEL … #define RGMII_CONFIG_BYPASS_TX_ID_EN … #define RGMII_CONFIG_LOOPBACK_EN … #define RGMII_CONFIG_PROG_SWAP … #define RGMII_CONFIG_DDR_MODE … #define RGMII_CONFIG_SGMII_CLK_DVDR … /* SDCC_HC_REG_DLL_CONFIG fields */ #define SDCC_DLL_CONFIG_DLL_RST … #define SDCC_DLL_CONFIG_PDN … #define SDCC_DLL_CONFIG_MCLK_FREQ … #define SDCC_DLL_CONFIG_CDR_SELEXT … #define SDCC_DLL_CONFIG_CDR_EXT_EN … #define SDCC_DLL_CONFIG_CK_OUT_EN … #define SDCC_DLL_CONFIG_CDR_EN … #define SDCC_DLL_CONFIG_DLL_EN … #define SDCC_DLL_MCLK_GATING_EN … #define SDCC_DLL_CDR_FINE_PHASE … /* SDCC_HC_REG_DDR_CONFIG fields */ #define SDCC_DDR_CONFIG_PRG_DLY_EN … #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY … #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE … #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN … #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT … #define SDCC_DDR_CONFIG_PRG_RCLK_DLY … /* SDCC_HC_REG_DLL_CONFIG2 fields */ #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS … #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC … #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL … #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW … #define SDCC_DLL_CONFIG2_DDR_CAL_EN … /* SDC4_STATUS bits */ #define SDC4_STATUS_DLL_LOCK … /* RGMII_IO_MACRO_CONFIG2 fields */ #define RGMII_CONFIG2_RSVD_CONFIG15 … #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG … #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN … #define RGMII_CONFIG2_CLK_DIVIDE_SEL … #define RGMII_CONFIG2_RX_PROG_SWAP … #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL … #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN … /* MAC_CTRL_REG bits */ #define ETHQOS_MAC_CTRL_SPEED_MODE … #define ETHQOS_MAC_CTRL_PORT_SEL … /* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */ #define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN … #define SGMII_10M_RX_CLK_DVDR … struct ethqos_emac_por { … }; struct ethqos_emac_driver_data { … }; struct qcom_ethqos { … }; static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) { … } static void rgmii_writel(struct qcom_ethqos *ethqos, int value, unsigned int offset) { … } static void rgmii_updatel(struct qcom_ethqos *ethqos, int mask, int val, unsigned int offset) { … } static void rgmii_dump(void *priv) { … } /* Clock rates */ #define RGMII_1000_NOM_CLK_FREQ … #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ … #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ … static void ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed) { … } static void qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable) { … } static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) { … } static const struct ethqos_emac_por emac_v2_3_0_por[] = …; static const struct ethqos_emac_driver_data emac_v2_3_0_data = …; static const struct ethqos_emac_por emac_v2_1_0_por[] = …; static const struct ethqos_emac_driver_data emac_v2_1_0_data = …; static const struct ethqos_emac_por emac_v3_0_0_por[] = …; static const struct ethqos_emac_driver_data emac_v3_0_0_data = …; static const struct ethqos_emac_por emac_v4_0_0_por[] = …; static const struct ethqos_emac_driver_data emac_v4_0_0_data = …; static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { … } static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) { … } static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos) { … } static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed) { … } /* On interface toggle MAC registers gets reset. * Configure MAC block for SGMII on ethernet phy link up */ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) { … } static void qcom_ethqos_speed_mode_2500(struct net_device *ndev, void *data) { … } static int ethqos_configure(struct qcom_ethqos *ethqos) { … } static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) { … } static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) { … } static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv) { … } static int ethqos_clks_config(void *priv, bool enabled) { … } static void ethqos_clks_disable(void *data) { … } static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) { … } static int qcom_ethqos_probe(struct platform_device *pdev) { … } static const struct of_device_id qcom_ethqos_match[] = …; MODULE_DEVICE_TABLE(of, qcom_ethqos_match); static struct platform_driver qcom_ethqos_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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