// SPDX-License-Identifier: GPL-2.0-only /* * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer * * Copyright (C) 2016 Martin Blumenstingl <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/ethtool.h> #include <linux/io.h> #include <linux/ioport.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_net.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/stmmac.h> #include "stmmac_platform.h" #define PRG_ETH0 … #define PRG_ETH0_RGMII_MODE … #define PRG_ETH0_EXT_PHY_MODE_MASK … #define PRG_ETH0_EXT_RGMII_MODE … #define PRG_ETH0_EXT_RMII_MODE … /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ #define PRG_ETH0_CLK_M250_SEL_MASK … /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one * cycle of the 125MHz RGMII TX clock): * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 */ #define PRG_ETH0_TXDLY_MASK … /* divider for the result of m250_sel */ #define PRG_ETH0_CLK_M250_DIV_SHIFT … #define PRG_ETH0_CLK_M250_DIV_WIDTH … #define PRG_ETH0_RGMII_TX_CLK_EN … #define PRG_ETH0_INVERTED_RMII_CLK … #define PRG_ETH0_TX_AND_PHY_REF_CLK … /* Bypass (= 0, the signal from the GPIO input directly connects to the * internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0] * timing tuning. */ #define PRG_ETH0_ADJ_ENABLE … /* Controls whether the RXEN and RXD[3:0] signals should be aligned with the * input RX rising/falling edge and sent to the Ethernet internals. This sets * the automatically delay and skew automatically (internally). */ #define PRG_ETH0_ADJ_SETUP … /* An internal counter based on the "timing-adjustment" clock. The counter is * cleared on both, the falling and rising edge of the RX_CLK. This selects the * delay (= the counter value) when to start sampling RXEN and RXD[3:0]. */ #define PRG_ETH0_ADJ_DELAY … /* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1, * ...) can be configured to be 1 to compensate for a delay of about 1ns. */ #define PRG_ETH0_ADJ_SKEW … #define PRG_ETH1 … /* Defined for adding a delay to the input RX_CLK for better timing. * Each step is 200ps. These bits are used with external RGMII PHYs * because RGMII RX only has the small window. cfg_rxclk_dly can * adjust the window between RX_CLK and RX_DATA and improve the stability * of "rx data valid". */ #define PRG_ETH1_CFG_RXCLK_DLY … struct meson8b_dwmac; struct meson8b_dwmac_data { … }; struct meson8b_dwmac { … }; struct meson8b_dwmac_clk_configs { … }; static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, u32 mask, u32 value) { … } static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, const char *name_suffix, const struct clk_parent_data *parents, int num_parents, const struct clk_ops *ops, struct clk_hw *hw) { … } static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) { … } static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac) { … } static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac) { … } static void meson8b_clk_disable_unprepare(void *data) { … } static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac, struct clk *clk) { … } static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac) { … } static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { … } static int meson8b_dwmac_probe(struct platform_device *pdev) { … } static const struct meson8b_dwmac_data meson8b_dwmac_data = …; static const struct meson8b_dwmac_data meson_axg_dwmac_data = …; static const struct meson8b_dwmac_data meson_g12a_dwmac_data = …; static const struct of_device_id meson8b_dwmac_match[] = …; MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); static struct platform_driver meson8b_dwmac_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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