linux/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 */
#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/stmmac.h>

#include "stmmac.h"
#include "stmmac_platform.h"

/* Peri Configuration register for mt2712 */
#define PERI_ETH_PHY_INTF_SEL …
#define PHY_INTF_MII …
#define PHY_INTF_RGMII …
#define PHY_INTF_RMII …
#define RMII_CLK_SRC_RXC …
#define RMII_CLK_SRC_INTERNAL …

#define PERI_ETH_DLY …
#define ETH_DLY_GTXC_INV …
#define ETH_DLY_GTXC_ENABLE …
#define ETH_DLY_GTXC_STAGES …
#define ETH_DLY_TXC_INV …
#define ETH_DLY_TXC_ENABLE …
#define ETH_DLY_TXC_STAGES …
#define ETH_DLY_RXC_INV …
#define ETH_DLY_RXC_ENABLE …
#define ETH_DLY_RXC_STAGES …

#define PERI_ETH_DLY_FINE …
#define ETH_RMII_DLY_TX_INV …
#define ETH_FINE_DLY_GTXC …
#define ETH_FINE_DLY_RXC …

/* Peri Configuration register for mt8195 */
#define MT8195_PERI_ETH_CTRL0 …
#define MT8195_RMII_CLK_SRC_INTERNAL …
#define MT8195_RMII_CLK_SRC_RXC …
#define MT8195_ETH_INTF_SEL …
#define MT8195_RGMII_TXC_PHASE_CTRL …
#define MT8195_EXT_PHY_MODE …
#define MT8195_DLY_GTXC_INV …
#define MT8195_DLY_GTXC_ENABLE …
#define MT8195_DLY_GTXC_STAGES …

#define MT8195_PERI_ETH_CTRL1 …
#define MT8195_DLY_RXC_INV …
#define MT8195_DLY_RXC_ENABLE …
#define MT8195_DLY_RXC_STAGES …
#define MT8195_DLY_TXC_INV …
#define MT8195_DLY_TXC_ENABLE …
#define MT8195_DLY_TXC_STAGES …

#define MT8195_PERI_ETH_CTRL2 …
#define MT8195_DLY_RMII_RXC_INV …
#define MT8195_DLY_RMII_RXC_ENABLE …
#define MT8195_DLY_RMII_RXC_STAGES …
#define MT8195_DLY_RMII_TXC_INV …
#define MT8195_DLY_RMII_TXC_ENABLE …
#define MT8195_DLY_RMII_TXC_STAGES …

struct mac_delay_struct { … };

struct mediatek_dwmac_plat_data { … };

struct mediatek_dwmac_variant { … };

/* list of clocks required for mac */
static const char * const mt2712_dwmac_clk_l[] = …;

static const char * const mt8195_dwmac_clk_l[] = …;

static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
{ … }

static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
{ … }

static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
{ … }

static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
{ … }

static const struct mediatek_dwmac_variant mt2712_gmac_variant = …;

static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
{ … }

static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
{ … }

static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
{ … }

static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
{ … }

static const struct mediatek_dwmac_variant mt8195_gmac_variant = …;

static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
{ … }

static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
{ … }

static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
{ … }

static int mediatek_dwmac_clks_config(void *priv, bool enabled)
{ … }

static int mediatek_dwmac_common_data(struct platform_device *pdev,
				      struct plat_stmmacenet_data *plat,
				      struct mediatek_dwmac_plat_data *priv_plat)
{ … }

static int mediatek_dwmac_probe(struct platform_device *pdev)
{ … }

static void mediatek_dwmac_remove(struct platform_device *pdev)
{ … }

static const struct of_device_id mediatek_dwmac_match[] = …;

MODULE_DEVICE_TABLE(of, mediatek_dwmac_match);

static struct platform_driver mediatek_dwmac_driver = …;
module_platform_driver(…) …;

MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;