// SPDX-License-Identifier: GPL-2.0-or-later /* * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer * * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited * Author: Srinivas Kandagatla <[email protected]> * Contributors: Giuseppe Cavallaro <[email protected]> */ #include <linux/kernel.h> #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/stmmac.h> #include <linux/phy.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/clk.h> #include <linux/of.h> #include <linux/of_net.h> #include "stmmac_platform.h" #define DWMAC_125MHZ … #define DWMAC_50MHZ … #define DWMAC_25MHZ … #define DWMAC_2_5MHZ … #define IS_PHY_IF_MODE_RGMII(iface) … #define IS_PHY_IF_MODE_GBIT(iface) … /* STiH4xx register definitions (STiH407/STiH410 families) * * Below table summarizes the clock requirement and clock sources for * supported phy interface modes with link speeds. * ________________________________________________ *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | * ------------------------------------------------ *| MII | n/a | 25Mhz | *| | | txclk | * ------------------------------------------------ *| GMII | 125Mhz | 25Mhz | *| | clk-125/txclk | txclk | * ------------------------------------------------ *| RGMII | 125Mhz | 25Mhz | *| | clk-125/txclk | clkgen | *| | clkgen | | * ------------------------------------------------ *| RMII | n/a | 25Mhz | *| | |clkgen/phyclk-in | * ------------------------------------------------ * * Register Configuration *------------------------------- * src |BIT(8)| BIT(7)| BIT(6)| *------------------------------- * txclk | 0 | n/a | 1 | *------------------------------- * ck_125| 0 | n/a | 0 | *------------------------------- * phyclk| 1 | 0 | n/a | *------------------------------- * clkgen| 1 | 1 | n/a | *------------------------------- */ #define STIH4XX_RETIME_SRC_MASK … #define STIH4XX_ETH_SEL_TX_RETIME_CLK … #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK … #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 … #define ENMII_MASK … #define ENMII … #define EN_MASK … #define EN … /* * 3 bits [4:2] * 000-GMII/MII * 001-RGMII * 010-SGMII * 100-RMII */ #define MII_PHY_SEL_MASK … #define ETH_PHY_SEL_RMII … #define ETH_PHY_SEL_SGMII … #define ETH_PHY_SEL_RGMII … #define ETH_PHY_SEL_GMII … #define ETH_PHY_SEL_MII … struct sti_dwmac { … }; struct sti_dwmac_of_data { … }; static u32 phy_intf_sels[] = …; enum { … }; static u32 stih4xx_tx_retime_val[] = …; static void stih4xx_fix_retime_src(void *priv, u32 spd, unsigned int mode) { … } static int sti_dwmac_set_mode(struct sti_dwmac *dwmac) { … } static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, struct platform_device *pdev) { … } static int sti_dwmac_probe(struct platform_device *pdev) { … } static void sti_dwmac_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int sti_dwmac_suspend(struct device *dev) { … } static int sti_dwmac_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, sti_dwmac_resume); static const struct sti_dwmac_of_data stih4xx_dwmac_data = …; static const struct of_device_id sti_dwmac_match[] = …; MODULE_DEVICE_TABLE(of, sti_dwmac_match); static struct platform_driver sti_dwmac_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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