// SPDX-License-Identifier: GPL-2.0-or-later /** * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer * * Copyright (C) 2014 Chen-Zhi (Roger Chen) * * Chen-Zhi (Roger Chen) <[email protected]> */ #include <linux/stmmac.h> #include <linux/bitops.h> #include <linux/clk.h> #include <linux/phy.h> #include <linux/of_net.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/pm_runtime.h> #include "stmmac_platform.h" struct rk_priv_data; struct rk_gmac_ops { … }; static const char * const rk_clocks[] = …; static const char * const rk_rmii_clocks[] = …; enum rk_clocks_index { … }; struct rk_priv_data { … }; #define HIWORD_UPDATE(val, mask, shift) … #define GRF_BIT(nr) … #define GRF_CLR_BIT(nr) … #define DELAY_ENABLE(soc, tx, rx) … #define PX30_GRF_GMAC_CON1 … /* PX30_GRF_GMAC_CON1 */ #define PX30_GMAC_PHY_INTF_SEL_RMII … #define PX30_GMAC_SPEED_10M … #define PX30_GMAC_SPEED_100M … static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops px30_ops = …; #define RK3128_GRF_MAC_CON0 … #define RK3128_GRF_MAC_CON1 … /* RK3128_GRF_MAC_CON0 */ #define RK3128_GMAC_TXCLK_DLY_ENABLE … #define RK3128_GMAC_TXCLK_DLY_DISABLE … #define RK3128_GMAC_RXCLK_DLY_ENABLE … #define RK3128_GMAC_RXCLK_DLY_DISABLE … #define RK3128_GMAC_CLK_RX_DL_CFG(val) … #define RK3128_GMAC_CLK_TX_DL_CFG(val) … /* RK3128_GRF_MAC_CON1 */ #define RK3128_GMAC_PHY_INTF_SEL_RGMII … #define RK3128_GMAC_PHY_INTF_SEL_RMII … #define RK3128_GMAC_FLOW_CTRL … #define RK3128_GMAC_FLOW_CTRL_CLR … #define RK3128_GMAC_SPEED_10M … #define RK3128_GMAC_SPEED_100M … #define RK3128_GMAC_RMII_CLK_25M … #define RK3128_GMAC_RMII_CLK_2_5M … #define RK3128_GMAC_CLK_125M … #define RK3128_GMAC_CLK_25M … #define RK3128_GMAC_CLK_2_5M … #define RK3128_GMAC_RMII_MODE … #define RK3128_GMAC_RMII_MODE_CLR … static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3128_ops = …; #define RK3228_GRF_MAC_CON0 … #define RK3228_GRF_MAC_CON1 … #define RK3228_GRF_CON_MUX … /* RK3228_GRF_MAC_CON0 */ #define RK3228_GMAC_CLK_RX_DL_CFG(val) … #define RK3228_GMAC_CLK_TX_DL_CFG(val) … /* RK3228_GRF_MAC_CON1 */ #define RK3228_GMAC_PHY_INTF_SEL_RGMII … #define RK3228_GMAC_PHY_INTF_SEL_RMII … #define RK3228_GMAC_FLOW_CTRL … #define RK3228_GMAC_FLOW_CTRL_CLR … #define RK3228_GMAC_SPEED_10M … #define RK3228_GMAC_SPEED_100M … #define RK3228_GMAC_RMII_CLK_25M … #define RK3228_GMAC_RMII_CLK_2_5M … #define RK3228_GMAC_CLK_125M … #define RK3228_GMAC_CLK_25M … #define RK3228_GMAC_CLK_2_5M … #define RK3228_GMAC_RMII_MODE … #define RK3228_GMAC_RMII_MODE_CLR … #define RK3228_GMAC_TXCLK_DLY_ENABLE … #define RK3228_GMAC_TXCLK_DLY_DISABLE … #define RK3228_GMAC_RXCLK_DLY_ENABLE … #define RK3228_GMAC_RXCLK_DLY_DISABLE … /* RK3228_GRF_COM_MUX */ #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY … static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) { … } static const struct rk_gmac_ops rk3228_ops = …; #define RK3288_GRF_SOC_CON1 … #define RK3288_GRF_SOC_CON3 … /*RK3288_GRF_SOC_CON1*/ #define RK3288_GMAC_PHY_INTF_SEL_RGMII … #define RK3288_GMAC_PHY_INTF_SEL_RMII … #define RK3288_GMAC_FLOW_CTRL … #define RK3288_GMAC_FLOW_CTRL_CLR … #define RK3288_GMAC_SPEED_10M … #define RK3288_GMAC_SPEED_100M … #define RK3288_GMAC_RMII_CLK_25M … #define RK3288_GMAC_RMII_CLK_2_5M … #define RK3288_GMAC_CLK_125M … #define RK3288_GMAC_CLK_25M … #define RK3288_GMAC_CLK_2_5M … #define RK3288_GMAC_RMII_MODE … #define RK3288_GMAC_RMII_MODE_CLR … /*RK3288_GRF_SOC_CON3*/ #define RK3288_GMAC_TXCLK_DLY_ENABLE … #define RK3288_GMAC_TXCLK_DLY_DISABLE … #define RK3288_GMAC_RXCLK_DLY_ENABLE … #define RK3288_GMAC_RXCLK_DLY_DISABLE … #define RK3288_GMAC_CLK_RX_DL_CFG(val) … #define RK3288_GMAC_CLK_TX_DL_CFG(val) … static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3288_ops = …; #define RK3308_GRF_MAC_CON0 … /* RK3308_GRF_MAC_CON0 */ #define RK3308_GMAC_PHY_INTF_SEL_RMII … #define RK3308_GMAC_FLOW_CTRL … #define RK3308_GMAC_FLOW_CTRL_CLR … #define RK3308_GMAC_SPEED_10M … #define RK3308_GMAC_SPEED_100M … static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3308_ops = …; #define RK3328_GRF_MAC_CON0 … #define RK3328_GRF_MAC_CON1 … #define RK3328_GRF_MAC_CON2 … #define RK3328_GRF_MACPHY_CON1 … /* RK3328_GRF_MAC_CON0 */ #define RK3328_GMAC_CLK_RX_DL_CFG(val) … #define RK3328_GMAC_CLK_TX_DL_CFG(val) … /* RK3328_GRF_MAC_CON1 */ #define RK3328_GMAC_PHY_INTF_SEL_RGMII … #define RK3328_GMAC_PHY_INTF_SEL_RMII … #define RK3328_GMAC_FLOW_CTRL … #define RK3328_GMAC_FLOW_CTRL_CLR … #define RK3328_GMAC_SPEED_10M … #define RK3328_GMAC_SPEED_100M … #define RK3328_GMAC_RMII_CLK_25M … #define RK3328_GMAC_RMII_CLK_2_5M … #define RK3328_GMAC_CLK_125M … #define RK3328_GMAC_CLK_25M … #define RK3328_GMAC_CLK_2_5M … #define RK3328_GMAC_RMII_MODE … #define RK3328_GMAC_RMII_MODE_CLR … #define RK3328_GMAC_TXCLK_DLY_ENABLE … #define RK3328_GMAC_TXCLK_DLY_DISABLE … #define RK3328_GMAC_RXCLK_DLY_ENABLE … #define RK3328_GMAC_RXCLK_DLY_DISABLE … /* RK3328_GRF_MACPHY_CON1 */ #define RK3328_MACPHY_RMII_MODE … static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) { … } static const struct rk_gmac_ops rk3328_ops = …; #define RK3366_GRF_SOC_CON6 … #define RK3366_GRF_SOC_CON7 … /* RK3366_GRF_SOC_CON6 */ #define RK3366_GMAC_PHY_INTF_SEL_RGMII … #define RK3366_GMAC_PHY_INTF_SEL_RMII … #define RK3366_GMAC_FLOW_CTRL … #define RK3366_GMAC_FLOW_CTRL_CLR … #define RK3366_GMAC_SPEED_10M … #define RK3366_GMAC_SPEED_100M … #define RK3366_GMAC_RMII_CLK_25M … #define RK3366_GMAC_RMII_CLK_2_5M … #define RK3366_GMAC_CLK_125M … #define RK3366_GMAC_CLK_25M … #define RK3366_GMAC_CLK_2_5M … #define RK3366_GMAC_RMII_MODE … #define RK3366_GMAC_RMII_MODE_CLR … /* RK3366_GRF_SOC_CON7 */ #define RK3366_GMAC_TXCLK_DLY_ENABLE … #define RK3366_GMAC_TXCLK_DLY_DISABLE … #define RK3366_GMAC_RXCLK_DLY_ENABLE … #define RK3366_GMAC_RXCLK_DLY_DISABLE … #define RK3366_GMAC_CLK_RX_DL_CFG(val) … #define RK3366_GMAC_CLK_TX_DL_CFG(val) … static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3366_ops = …; #define RK3368_GRF_SOC_CON15 … #define RK3368_GRF_SOC_CON16 … /* RK3368_GRF_SOC_CON15 */ #define RK3368_GMAC_PHY_INTF_SEL_RGMII … #define RK3368_GMAC_PHY_INTF_SEL_RMII … #define RK3368_GMAC_FLOW_CTRL … #define RK3368_GMAC_FLOW_CTRL_CLR … #define RK3368_GMAC_SPEED_10M … #define RK3368_GMAC_SPEED_100M … #define RK3368_GMAC_RMII_CLK_25M … #define RK3368_GMAC_RMII_CLK_2_5M … #define RK3368_GMAC_CLK_125M … #define RK3368_GMAC_CLK_25M … #define RK3368_GMAC_CLK_2_5M … #define RK3368_GMAC_RMII_MODE … #define RK3368_GMAC_RMII_MODE_CLR … /* RK3368_GRF_SOC_CON16 */ #define RK3368_GMAC_TXCLK_DLY_ENABLE … #define RK3368_GMAC_TXCLK_DLY_DISABLE … #define RK3368_GMAC_RXCLK_DLY_ENABLE … #define RK3368_GMAC_RXCLK_DLY_DISABLE … #define RK3368_GMAC_CLK_RX_DL_CFG(val) … #define RK3368_GMAC_CLK_TX_DL_CFG(val) … static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3368_ops = …; #define RK3399_GRF_SOC_CON5 … #define RK3399_GRF_SOC_CON6 … /* RK3399_GRF_SOC_CON5 */ #define RK3399_GMAC_PHY_INTF_SEL_RGMII … #define RK3399_GMAC_PHY_INTF_SEL_RMII … #define RK3399_GMAC_FLOW_CTRL … #define RK3399_GMAC_FLOW_CTRL_CLR … #define RK3399_GMAC_SPEED_10M … #define RK3399_GMAC_SPEED_100M … #define RK3399_GMAC_RMII_CLK_25M … #define RK3399_GMAC_RMII_CLK_2_5M … #define RK3399_GMAC_CLK_125M … #define RK3399_GMAC_CLK_25M … #define RK3399_GMAC_CLK_2_5M … #define RK3399_GMAC_RMII_MODE … #define RK3399_GMAC_RMII_MODE_CLR … /* RK3399_GRF_SOC_CON6 */ #define RK3399_GMAC_TXCLK_DLY_ENABLE … #define RK3399_GMAC_TXCLK_DLY_DISABLE … #define RK3399_GMAC_RXCLK_DLY_ENABLE … #define RK3399_GMAC_RXCLK_DLY_DISABLE … #define RK3399_GMAC_CLK_RX_DL_CFG(val) … #define RK3399_GMAC_CLK_TX_DL_CFG(val) … static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3399_ops = …; #define RK3568_GRF_GMAC0_CON0 … #define RK3568_GRF_GMAC0_CON1 … #define RK3568_GRF_GMAC1_CON0 … #define RK3568_GRF_GMAC1_CON1 … /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ #define RK3568_GMAC_PHY_INTF_SEL_RGMII … #define RK3568_GMAC_PHY_INTF_SEL_RMII … #define RK3568_GMAC_FLOW_CTRL … #define RK3568_GMAC_FLOW_CTRL_CLR … #define RK3568_GMAC_RXCLK_DLY_ENABLE … #define RK3568_GMAC_RXCLK_DLY_DISABLE … #define RK3568_GMAC_TXCLK_DLY_ENABLE … #define RK3568_GMAC_TXCLK_DLY_DISABLE … /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ #define RK3568_GMAC_CLK_RX_DL_CFG(val) … #define RK3568_GMAC_CLK_TX_DL_CFG(val) … static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rk3568_ops = …; /* sys_grf */ #define RK3588_GRF_GMAC_CON7 … #define RK3588_GRF_GMAC_CON8 … #define RK3588_GRF_GMAC_CON9 … #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) … #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) … #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) … #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) … #define RK3588_GMAC_CLK_RX_DL_CFG(val) … #define RK3588_GMAC_CLK_TX_DL_CFG(val) … /* php_grf */ #define RK3588_GRF_GMAC_CON0 … #define RK3588_GRF_CLK_CON1 … #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) … #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) … #define RK3588_GMAC_CLK_RMII_MODE(id) … #define RK3588_GMAC_CLK_RGMII_MODE(id) … #define RK3588_GMAC_CLK_SELET_CRU(id) … #define RK3588_GMAC_CLK_SELET_IO(id) … #define RK3588_GMA_CLK_RMII_DIV2(id) … #define RK3588_GMA_CLK_RMII_DIV20(id) … #define RK3588_GMAC_CLK_RGMII_DIV1(id) … #define RK3588_GMAC_CLK_RGMII_DIV5(id) … #define RK3588_GMAC_CLK_RGMII_DIV50(id) … #define RK3588_GMAC_CLK_RMII_GATE(id) … #define RK3588_GMAC_CLK_RMII_NOGATE(id) … static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, bool enable) { … } static const struct rk_gmac_ops rk3588_ops = …; #define RV1108_GRF_GMAC_CON0 … /* RV1108_GRF_GMAC_CON0 */ #define RV1108_GMAC_PHY_INTF_SEL_RMII … #define RV1108_GMAC_FLOW_CTRL … #define RV1108_GMAC_FLOW_CTRL_CLR … #define RV1108_GMAC_SPEED_10M … #define RV1108_GMAC_SPEED_100M … #define RV1108_GMAC_RMII_CLK_25M … #define RV1108_GMAC_RMII_CLK_2_5M … static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rv1108_ops = …; #define RV1126_GRF_GMAC_CON0 … #define RV1126_GRF_GMAC_CON1 … #define RV1126_GRF_GMAC_CON2 … /* RV1126_GRF_GMAC_CON0 */ #define RV1126_GMAC_PHY_INTF_SEL_RGMII … #define RV1126_GMAC_PHY_INTF_SEL_RMII … #define RV1126_GMAC_FLOW_CTRL … #define RV1126_GMAC_FLOW_CTRL_CLR … #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE … #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE … #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE … #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE … #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE … #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE … #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE … #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE … /* RV1126_GRF_GMAC_CON1 */ #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) … #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) … /* RV1126_GRF_GMAC_CON2 */ #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) … #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) … static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, int tx_delay, int rx_delay) { … } static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) { … } static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) { … } static const struct rk_gmac_ops rv1126_ops = …; #define RK_GRF_MACPHY_CON0 … #define RK_GRF_MACPHY_CON1 … #define RK_GRF_MACPHY_CON2 … #define RK_GRF_MACPHY_CON3 … #define RK_MACPHY_ENABLE … #define RK_MACPHY_DISABLE … #define RK_MACPHY_CFG_CLK_50M … #define RK_GMAC2PHY_RMII_MODE … #define RK_GRF_CON2_MACPHY_ID … #define RK_GRF_CON3_MACPHY_ID … static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) { … } static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) { … } static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) { … } static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) { … } static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) { … } static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, struct plat_stmmacenet_data *plat, const struct rk_gmac_ops *ops) { … } static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) { … } static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) { … } static void rk_gmac_powerdown(struct rk_priv_data *gmac) { … } static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode) { … } static int rk_gmac_probe(struct platform_device *pdev) { … } static void rk_gmac_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int rk_gmac_suspend(struct device *dev) { … } static int rk_gmac_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); static const struct of_device_id rk_gmac_dwmac_match[] = …; MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); static struct platform_driver rk_gmac_dwmac_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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