// SPDX-License-Identifier: GPL-2.0-only /* * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU * * Copyright (C) STMicroelectronics SA 2017 * Author: Alexandre Torgue <[email protected]> for STMicroelectronics. */ #include <linux/clk.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_net.h> #include <linux/phy.h> #include <linux/platform_device.h> #include <linux/pm_wakeirq.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/stmmac.h> #include "stmmac_platform.h" #define SYSCFG_MCU_ETH_MASK … #define SYSCFG_MP1_ETH_MASK … #define SYSCFG_PMCCLRR_OFFSET … #define SYSCFG_PMCR_ETH_CLK_SEL … #define SYSCFG_PMCR_ETH_REF_CLK_SEL … /* CLOCK feed to PHY*/ #define ETH_CK_F_25M … #define ETH_CK_F_50M … #define ETH_CK_F_125M … /* Ethernet PHY interface selection in register SYSCFG Configuration *------------------------------------------ * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)| *------------------------------------------ * MII | 0 | 0 | 0 | 1 | *------------------------------------------ * GMII | 0 | 0 | 0 | 0 | *------------------------------------------ * RGMII | 0 | 0 | 1 | n/a | *------------------------------------------ * RMII | 1 | 0 | 0 | n/a | *------------------------------------------ */ #define SYSCFG_PMCR_ETH_SEL_MII … #define SYSCFG_PMCR_ETH_SEL_RGMII … #define SYSCFG_PMCR_ETH_SEL_RMII … #define SYSCFG_PMCR_ETH_SEL_GMII … #define SYSCFG_MCU_ETH_SEL_MII … #define SYSCFG_MCU_ETH_SEL_RMII … /* STM32MP2 register definitions */ #define SYSCFG_MP2_ETH_MASK … #define SYSCFG_ETHCR_ETH_PTP_CLK_SEL … #define SYSCFG_ETHCR_ETH_CLK_SEL … #define SYSCFG_ETHCR_ETH_REF_CLK_SEL … #define SYSCFG_ETHCR_ETH_SEL_MII … #define SYSCFG_ETHCR_ETH_SEL_RGMII … #define SYSCFG_ETHCR_ETH_SEL_RMII … /* STM32MPx register definitions * * Below table summarizes the clock requirement and clock sources for * supported phy interface modes. * __________________________________________________________________________ *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY| *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | *| | | st,ext-phyclk | | | * --------------------------------------------------------------------------- *| GMII | - | eth-ck | n/a | n/a | *| | | st,ext-phyclk | | | * --------------------------------------------------------------------------- *| RGMII | - | eth-ck | n/a | eth-ck | *| | | st,ext-phyclk | | st,eth-clk-sel or| *| | | | | st,ext-phyclk | * --------------------------------------------------------------------------- *| RMII | - | eth-ck | eth-ck | n/a | *| | | st,ext-phyclk | st,eth-ref-clk-sel | | *| | | | or st,ext-phyclk | | * --------------------------------------------------------------------------- * */ struct stm32_dwmac { … }; struct stm32_ops { … }; static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) { … } static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume) { … } static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) { … } static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) { … } static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) { … } static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) { … } static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) { … } static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) { … } static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend) { … } static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, struct device *dev) { … } static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, struct device *dev) { … } static int stm32_dwmac_probe(struct platform_device *pdev) { … } static void stm32_dwmac_remove(struct platform_device *pdev) { … } static int stm32mp1_suspend(struct stm32_dwmac *dwmac) { … } static void stm32mp1_resume(struct stm32_dwmac *dwmac) { … } #ifdef CONFIG_PM_SLEEP static int stm32_dwmac_suspend(struct device *dev) { … } static int stm32_dwmac_resume(struct device *dev) { … } #endif /* CONFIG_PM_SLEEP */ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, stm32_dwmac_suspend, stm32_dwmac_resume); static struct stm32_ops stm32mcu_dwmac_data = …; static struct stm32_ops stm32mp1_dwmac_data = …; static struct stm32_ops stm32mp13_dwmac_data = …; static struct stm32_ops stm32mp25_dwmac_data = …; static const struct of_device_id stm32_dwmac_match[] = …; MODULE_DEVICE_TABLE(of, stm32_dwmac_match); static struct platform_driver stm32_dwmac_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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