linux/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
 *
 * Copyright 2020 NXP
 *
 */

#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/stmmac.h>

#include "stmmac_platform.h"

#define GPR_ENET_QOS_INTF_MODE_MASK …
#define GPR_ENET_QOS_INTF_SEL_MII …
#define GPR_ENET_QOS_INTF_SEL_RMII …
#define GPR_ENET_QOS_INTF_SEL_RGMII …
#define GPR_ENET_QOS_CLK_GEN_EN …
#define GPR_ENET_QOS_CLK_TX_CLK_SEL …
#define GPR_ENET_QOS_RGMII_EN …

#define MX93_GPR_ENET_QOS_INTF_MODE_MASK …
#define MX93_GPR_ENET_QOS_INTF_MASK …
#define MX93_GPR_ENET_QOS_INTF_SEL_MII …
#define MX93_GPR_ENET_QOS_INTF_SEL_RMII …
#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII …
#define MX93_GPR_ENET_QOS_CLK_GEN_EN …

#define DMA_BUS_MODE …
#define DMA_BUS_MODE_SFT_RESET …
#define RMII_RESET_SPEED …
#define CTRL_SPEED_MASK …

struct imx_dwmac_ops { … };

struct imx_priv_data { … };

static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
{
	struct imx_priv_data *dwmac = plat_dat->bsp_priv;
	int val;

	switch (plat_dat->mac_interface) {
	case PHY_INTERFACE_MODE_MII:
		val = GPR_ENET_QOS_INTF_SEL_MII;
		break;
	case PHY_INTERFACE_MODE_RMII:
		val = GPR_ENET_QOS_INTF_SEL_RMII;
		val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
		break;
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		val = GPR_ENET_QOS_INTF_SEL_RGMII |
		      GPR_ENET_QOS_RGMII_EN;
		break;
	default:
		pr_debug("imx dwmac doesn't support %d interface\n",
			 plat_dat->mac_interface);
		return -EINVAL;
	}

	val |= GPR_ENET_QOS_CLK_GEN_EN;
	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
				  GPR_ENET_QOS_INTF_MODE_MASK, val);
};

static int
imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
{ … }

static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
{
	struct imx_priv_data *dwmac = plat_dat->bsp_priv;
	int val;

	switch (plat_dat->mac_interface) {
	case PHY_INTERFACE_MODE_MII:
		val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
		break;
	case PHY_INTERFACE_MODE_RMII:
		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
		break;
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
		break;
	default:
		dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
			 plat_dat->mac_interface);
		return -EINVAL;
	}

	val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
				  MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
};

static int imx_dwmac_clks_config(void *priv, bool enabled)
{ … }

static int imx_dwmac_init(struct platform_device *pdev, void *priv)
{ … }

static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
{ … }

static void imx_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
{ … }

static void imx93_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
{ … }

static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
{ … }

static int
imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
{ … }

static int imx_dwmac_probe(struct platform_device *pdev)
{ … }

static struct imx_dwmac_ops imx8mp_dwmac_data = …;

static struct imx_dwmac_ops imx8dxl_dwmac_data = …;

static struct imx_dwmac_ops imx93_dwmac_data = …;

static const struct of_device_id imx_dwmac_match[] = …;
MODULE_DEVICE_TABLE(of, imx_dwmac_match);

static struct platform_driver imx_dwmac_driver = …;
module_platform_driver(…) …;

MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;