/* SPDX-License-Identifier: GPL-2.0 */ /* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $ * sungem.h: Definitions for Sun GEM ethernet driver. * * Copyright (C) 2000 David S. Miller ([email protected]) */ #ifndef _SUNGEM_H #define _SUNGEM_H /* Global Registers */ #define GREG_SEBSTATE … #define GREG_CFG … #define GREG_STAT … #define GREG_IMASK … #define GREG_IACK … #define GREG_STAT2 … #define GREG_PCIESTAT … #define GREG_PCIEMASK … #define GREG_BIFCFG … #define GREG_BIFDIAG … #define GREG_SWRST … /* Global SEB State Register */ #define GREG_SEBSTATE_ARB … #define GREG_SEBSTATE_RXWON … /* Global Configuration Register */ #define GREG_CFG_IBURST … #define GREG_CFG_TXDMALIM … #define GREG_CFG_RXDMALIM … #define GREG_CFG_RONPAULBIT … #define GREG_CFG_ENBUG2FIX … /* Global Interrupt Status Register. * * Reading this register automatically clears bits 0 through 6. * This auto-clearing does not occur when the alias at GREG_STAT2 * is read instead. The rest of the interrupt bits only clear when * the secondary interrupt status register corresponding to that * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by * reading PCS_ISTAT). */ #define GREG_STAT_TXINTME … #define GREG_STAT_TXALL … #define GREG_STAT_TXDONE … #define GREG_STAT_RXDONE … #define GREG_STAT_RXNOBUF … #define GREG_STAT_RXTAGERR … #define GREG_STAT_PCS … #define GREG_STAT_TXMAC … #define GREG_STAT_RXMAC … #define GREG_STAT_MAC … #define GREG_STAT_MIF … #define GREG_STAT_PCIERR … #define GREG_STAT_TXNR … #define GREG_STAT_TXNR_SHIFT … #define GREG_STAT_ABNORMAL … #define GREG_STAT_NAPI … /* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT. * Bits set in GREG_IMASK will prevent that interrupt type from being * signalled to the cpu. GREG_IACK can be used to clear specific top-level * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6. * Setting the bit will clear that interrupt, clear bits will have no effect * on GREG_STAT. */ /* Global PCI Error Status Register */ #define GREG_PCIESTAT_BADACK … #define GREG_PCIESTAT_DTRTO … #define GREG_PCIESTAT_OTHER … /* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT. * Bits set in GREG_PCIEMASK will prevent that interrupt type from being * signalled to the cpu. */ /* Global BIF Configuration Register */ #define GREG_BIFCFG_SLOWCLK … #define GREG_BIFCFG_B64DIS … #define GREG_BIFCFG_M66EN … /* Global BIF Diagnostics Register */ #define GREG_BIFDIAG_BURSTSM … #define GREG_BIFDIAG_BIFSM … /* Global Software Reset Register. * * This register is used to perform a global reset of the RX and TX portions * of the GEM asic. Setting the RX or TX reset bit will start the reset. * The driver _MUST_ poll these bits until they clear. One may not attempt * to program any other part of GEM until the bits clear. */ #define GREG_SWRST_TXRST … #define GREG_SWRST_RXRST … #define GREG_SWRST_RSTOUT … #define GREG_SWRST_CACHESIZE … #define GREG_SWRST_CACHE_SHIFT … /* TX DMA Registers */ #define TXDMA_KICK … #define TXDMA_CFG … #define TXDMA_DBLOW … #define TXDMA_DBHI … #define TXDMA_FWPTR … #define TXDMA_FSWPTR … #define TXDMA_FRPTR … #define TXDMA_FSRPTR … #define TXDMA_PCNT … #define TXDMA_SMACHINE … #define TXDMA_DPLOW … #define TXDMA_DPHI … #define TXDMA_TXDONE … #define TXDMA_FADDR … #define TXDMA_FTAG … #define TXDMA_DLOW … #define TXDMA_DHIT1 … #define TXDMA_DHIT0 … #define TXDMA_FSZ … /* TX Kick Register. * * This 13-bit register is programmed by the driver to hold the descriptor * entry index which follows the last valid transmit descriptor. */ /* TX Completion Register. * * This 13-bit register is updated by GEM to hold to descriptor entry index * which follows the last descriptor already processed by GEM. Note that * this value is mirrored in GREG_STAT which eliminates the need to even * access this register in the driver during interrupt processing. */ /* TX Configuration Register. * * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature * that was meant to be used with jumbo packets. It should be set to the * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors. */ #define TXDMA_CFG_ENABLE … #define TXDMA_CFG_RINGSZ … #define TXDMA_CFG_RINGSZ_32 … #define TXDMA_CFG_RINGSZ_64 … #define TXDMA_CFG_RINGSZ_128 … #define TXDMA_CFG_RINGSZ_256 … #define TXDMA_CFG_RINGSZ_512 … #define TXDMA_CFG_RINGSZ_1K … #define TXDMA_CFG_RINGSZ_2K … #define TXDMA_CFG_RINGSZ_4K … #define TXDMA_CFG_RINGSZ_8K … #define TXDMA_CFG_PIOSEL … #define TXDMA_CFG_FTHRESH … #define TXDMA_CFG_PMODE … /* TX Descriptor Base Low/High. * * These two registers store the 53 most significant bits of the base address * of the TX descriptor table. The 11 least significant bits are always * zero. As a result, the TX descriptor table must be 2K aligned. */ /* The rest of the TXDMA_* registers are for diagnostics and debug, I will document * them later. -DaveM */ /* WakeOnLan Registers */ #define WOL_MATCH0 … #define WOL_MATCH1 … #define WOL_MATCH2 … #define WOL_MCOUNT … #define WOL_WAKECSR … /* WOL Match count register */ #define WOL_MCOUNT_N … #define WOL_MCOUNT_M … #define WOL_WAKECSR_ENABLE … #define WOL_WAKECSR_MII … #define WOL_WAKECSR_SEEN … #define WOL_WAKECSR_FILT_UCAST … #define WOL_WAKECSR_FILT_MCAST … #define WOL_WAKECSR_FILT_BCAST … #define WOL_WAKECSR_FILT_SEEN … /* Receive DMA Registers */ #define RXDMA_CFG … #define RXDMA_DBLOW … #define RXDMA_DBHI … #define RXDMA_FWPTR … #define RXDMA_FSWPTR … #define RXDMA_FRPTR … #define RXDMA_PCNT … #define RXDMA_SMACHINE … #define RXDMA_PTHRESH … #define RXDMA_DPLOW … #define RXDMA_DPHI … #define RXDMA_KICK … #define RXDMA_DONE … #define RXDMA_BLANK … #define RXDMA_FADDR … #define RXDMA_FTAG … #define RXDMA_DLOW … #define RXDMA_DHIT1 … #define RXDMA_DHIT0 … #define RXDMA_FSZ … /* RX Configuration Register. */ #define RXDMA_CFG_ENABLE … #define RXDMA_CFG_RINGSZ … #define RXDMA_CFG_RINGSZ_32 … #define RXDMA_CFG_RINGSZ_64 … #define RXDMA_CFG_RINGSZ_128 … #define RXDMA_CFG_RINGSZ_256 … #define RXDMA_CFG_RINGSZ_512 … #define RXDMA_CFG_RINGSZ_1K … #define RXDMA_CFG_RINGSZ_2K … #define RXDMA_CFG_RINGSZ_4K … #define RXDMA_CFG_RINGSZ_8K … #define RXDMA_CFG_RINGSZ_BDISAB … #define RXDMA_CFG_FBOFF … #define RXDMA_CFG_CSUMOFF … #define RXDMA_CFG_FTHRESH … #define RXDMA_CFG_FTHRESH_64 … #define RXDMA_CFG_FTHRESH_128 … #define RXDMA_CFG_FTHRESH_256 … #define RXDMA_CFG_FTHRESH_512 … #define RXDMA_CFG_FTHRESH_1K … #define RXDMA_CFG_FTHRESH_2K … /* RX Descriptor Base Low/High. * * These two registers store the 53 most significant bits of the base address * of the RX descriptor table. The 11 least significant bits are always * zero. As a result, the RX descriptor table must be 2K aligned. */ /* RX PAUSE Thresholds. * * These values determine when XOFF and XON PAUSE frames are emitted by * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes. */ #define RXDMA_PTHRESH_OFF … #define RXDMA_PTHRESH_ON … /* RX Kick Register. * * This 13-bit register is written by the host CPU and holds the last * valid RX descriptor number plus one. This is, if 'N' is written to * this register, it means that all RX descriptors up to but excluding * 'N' are valid. * * The hardware requires that RX descriptors are posted in increments * of 4. This means 'N' must be a multiple of four. For the best * performance, the first new descriptor being posted should be (PCI) * cache line aligned. */ /* RX Completion Register. * * This 13-bit register is updated by GEM to indicate which RX descriptors * have already been used for receive frames. All descriptors up to but * excluding the value in this register are ready to be processed. GEM * updates this register value after the RX FIFO empties completely into * the RX descriptor's buffer, but before the RX_DONE bit is set in the * interrupt status register. */ /* RX Blanking Register. */ #define RXDMA_BLANK_IPKTS … #define RXDMA_BLANK_ITIME … /* RX FIFO Size. * * This 11-bit read-only register indicates how large, in units of 64-bytes, * the RX FIFO is. The driver uses this to properly configure the RX PAUSE * thresholds. */ /* The rest of the RXDMA_* registers are for diagnostics and debug, I will document * them later. -DaveM */ /* MAC Registers */ #define MAC_TXRST … #define MAC_RXRST … #define MAC_SNDPAUSE … #define MAC_TXSTAT … #define MAC_RXSTAT … #define MAC_CSTAT … #define MAC_TXMASK … #define MAC_RXMASK … #define MAC_MCMASK … #define MAC_TXCFG … #define MAC_RXCFG … #define MAC_MCCFG … #define MAC_XIFCFG … #define MAC_IPG0 … #define MAC_IPG1 … #define MAC_IPG2 … #define MAC_STIME … #define MAC_MINFSZ … #define MAC_MAXFSZ … #define MAC_PASIZE … #define MAC_JAMSIZE … #define MAC_ATTLIM … #define MAC_MCTYPE … #define MAC_ADDR0 … #define MAC_ADDR1 … #define MAC_ADDR2 … #define MAC_ADDR3 … #define MAC_ADDR4 … #define MAC_ADDR5 … #define MAC_ADDR6 … #define MAC_ADDR7 … #define MAC_ADDR8 … #define MAC_AFILT0 … #define MAC_AFILT1 … #define MAC_AFILT2 … #define MAC_AF21MSK … #define MAC_AF0MSK … #define MAC_HASH0 … #define MAC_HASH1 … #define MAC_HASH2 … #define MAC_HASH3 … #define MAC_HASH4 … #define MAC_HASH5 … #define MAC_HASH6 … #define MAC_HASH7 … #define MAC_HASH8 … #define MAC_HASH9 … #define MAC_HASH10 … #define MAC_HASH11 … #define MAC_HASH12 … #define MAC_HASH13 … #define MAC_HASH14 … #define MAC_HASH15 … #define MAC_NCOLL … #define MAC_FASUCC … #define MAC_ECOLL … #define MAC_LCOLL … #define MAC_DTIMER … #define MAC_PATMPS … #define MAC_RFCTR … #define MAC_LERR … #define MAC_AERR … #define MAC_FCSERR … #define MAC_RXCVERR … #define MAC_RANDSEED … #define MAC_SMACHINE … /* TX MAC Software Reset Command. */ #define MAC_TXRST_CMD … /* RX MAC Software Reset Command. */ #define MAC_RXRST_CMD … /* Send Pause Command. */ #define MAC_SNDPAUSE_TS … #define MAC_SNDPAUSE_SP … /* TX MAC Status Register. */ #define MAC_TXSTAT_XMIT … #define MAC_TXSTAT_URUN … #define MAC_TXSTAT_MPE … #define MAC_TXSTAT_NCE … #define MAC_TXSTAT_ECE … #define MAC_TXSTAT_LCE … #define MAC_TXSTAT_FCE … #define MAC_TXSTAT_DTE … #define MAC_TXSTAT_PCE … /* RX MAC Status Register. */ #define MAC_RXSTAT_RCV … #define MAC_RXSTAT_OFLW … #define MAC_RXSTAT_FCE … #define MAC_RXSTAT_ACE … #define MAC_RXSTAT_CCE … #define MAC_RXSTAT_LCE … #define MAC_RXSTAT_VCE … /* MAC Control Status Register. */ #define MAC_CSTAT_PRCV … #define MAC_CSTAT_PS … #define MAC_CSTAT_NPS … #define MAC_CSTAT_PTR … /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent * that interrupt type from being signalled to front end of GEM. For * the interrupt to actually get sent to the cpu, it is necessary to * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well. */ /* TX MAC Configuration Register. * * NOTE: The TX MAC Enable bit must be cleared and polled until * zero before any other bits in this register are changed. * * Also, enabling the Carrier Extension feature of GEM is * a 3 step process 1) Set TX Carrier Extension 2) Set * RX Carrier Extension 3) Set Slot Time to 0x200. This * mode must be enabled when in half-duplex at 1Gbps, else * it must be disabled. */ #define MAC_TXCFG_ENAB … #define MAC_TXCFG_ICS … #define MAC_TXCFG_ICOLL … #define MAC_TXCFG_EIPG0 … #define MAC_TXCFG_NGU … #define MAC_TXCFG_NGUL … #define MAC_TXCFG_NBO … #define MAC_TXCFG_SD … #define MAC_TXCFG_NFCS … #define MAC_TXCFG_TCE … /* RX MAC Configuration Register. * * NOTE: The RX MAC Enable bit must be cleared and polled until * zero before any other bits in this register are changed. * * Similar rules apply to the Hash Filter Enable bit when * programming the hash table registers, and the Address Filter * Enable bit when programming the address filter registers. */ #define MAC_RXCFG_ENAB … #define MAC_RXCFG_SPAD … #define MAC_RXCFG_SFCS … #define MAC_RXCFG_PROM … #define MAC_RXCFG_PGRP … #define MAC_RXCFG_HFE … #define MAC_RXCFG_AFE … #define MAC_RXCFG_DDE … #define MAC_RXCFG_RCE … /* MAC Control Config Register. */ #define MAC_MCCFG_SPE … #define MAC_MCCFG_RPE … #define MAC_MCCFG_PMC … /* XIF Configuration Register. * * NOTE: When leaving or entering loopback mode, a global hardware * init of GEM should be performed. */ #define MAC_XIFCFG_OE … #define MAC_XIFCFG_LBCK … #define MAC_XIFCFG_DISE … #define MAC_XIFCFG_GMII … #define MAC_XIFCFG_MBOE … #define MAC_XIFCFG_LLED … #define MAC_XIFCFG_FLED … /* InterPacketGap0 Register. This 8-bit value is used as an extension * to the InterPacketGap1 Register. Specifically it contributes to the * timing of the RX-to-TX IPG. This value is ignored and presumed to * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit * is cleared in the TX MAC Configuration Register. * * This value in this register in terms of media byte time. * * Recommended value: 0x00 */ /* InterPacketGap1 Register. This 8-bit value defines the first 2/3 * portion of the Inter Packet Gap. * * This value in this register in terms of media byte time. * * Recommended value: 0x08 */ /* InterPacketGap2 Register. This 8-bit value defines the second 1/3 * portion of the Inter Packet Gap. * * This value in this register in terms of media byte time. * * Recommended value: 0x04 */ /* Slot Time Register. This 10-bit value specifies the slot time * parameter in units of media byte time. It determines the physical * span of the network. * * Recommended value: 0x40 */ /* Minimum Frame Size Register. This 10-bit register specifies the * smallest sized frame the TXMAC will send onto the medium, and the * RXMAC will receive from the medium. * * Recommended value: 0x40 */ /* Maximum Frame and Burst Size Register. * * This register specifies two things. First it specifies the maximum * sized frame the TXMAC will send and the RXMAC will recognize as * valid. Second, it specifies the maximum run length of a burst of * packets sent in half-duplex gigabit modes. * * Recommended value: 0x200005ee */ #define MAC_MAXFSZ_MFS … #define MAC_MAXFSZ_MBS … /* PA Size Register. This 10-bit register specifies the number of preamble * bytes which will be transmitted at the beginning of each frame. A * value of two or greater should be programmed here. * * Recommended value: 0x07 */ /* Jam Size Register. This 4-bit register specifies the duration of * the jam in units of media byte time. * * Recommended value: 0x04 */ /* Attempts Limit Register. This 8-bit register specifies the number * of attempts that the TXMAC will make to transmit a frame, before it * resets its Attempts Counter. After reaching the Attempts Limit the * TXMAC may or may not drop the frame, as determined by the NGU * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC * Configuration Register. * * Recommended value: 0x10 */ /* MAX Control Type Register. This 16-bit register specifies the * "type" field of a MAC Control frame. The TXMAC uses this field to * encapsulate the MAC Control frame for transmission, and the RXMAC * uses it for decoding valid MAC Control frames received from the * network. * * Recommended value: 0x8808 */ /* MAC Address Registers. Each of these registers specify the * ethernet MAC of the interface, 16-bits at a time. Register * 0 specifies bits [47:32], register 1 bits [31:16], and register * 2 bits [15:0]. * * Registers 3 through and including 5 specify an alternate * MAC address for the interface. * * Registers 6 through and including 8 specify the MAC Control * Address, which must be the reserved multicast address for MAC * Control frames. * * Example: To program primary station address a:b:c:d:e:f into * the chip. * MAC_Address_2 = (a << 8) | b * MAC_Address_1 = (c << 8) | d * MAC_Address_0 = (e << 8) | f */ /* Address Filter Registers. Registers 0 through 2 specify bit * fields [47:32] through [15:0], respectively, of the address * filter. The Address Filter 2&1 Mask Register denotes the 8-bit * nibble mask for Address Filter Registers 2 and 1. The Address * Filter 0 Mask Register denotes the 16-bit mask for the Address * Filter Register 0. */ /* Hash Table Registers. Registers 0 through 15 specify bit fields * [255:240] through [15:0], respectively, of the hash table. */ /* Statistics Registers. All of these registers are 16-bits and * track occurrences of a specific event. GEM can be configured * to interrupt the host cpu when any of these counters overflow. * They should all be explicitly initialized to zero when the interface * is brought up. */ /* Random Number Seed Register. This 10-bit value is used as the * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is * recommended to program this register to the 10 LSB of the * interfaces MAC address. */ /* Pause Timer, read-only. This 16-bit timer is used to time the pause * interval as indicated by a received pause flow control frame. * A non-zero value in this timer indicates that the MAC is currently in * the paused state. */ /* MIF Registers */ #define MIF_BBCLK … #define MIF_BBDATA … #define MIF_BBOENAB … #define MIF_FRAME … #define MIF_CFG … #define MIF_MASK … #define MIF_STATUS … #define MIF_SMACHINE … /* MIF Bit-Bang Clock. This 1-bit register is used to generate the * MDC clock waveform on the MII Management Interface when the MIF is * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into * this register will create a rising edge on the MDC, while writing * a '0' after a '1' will create a falling edge. For every bit that * is transferred on the management interface, both edges have to be * generated. */ /* MIF Bit-Bang Data. This 1-bit register is used to generate the * outgoing data (MDO) on the MII Management Interface when the MIF * is programmed in the "Bit-Bang" mode. The daa will be steered to the * appropriate MDIO based on the state of the PHY_Select bit in the MIF * Configuration Register. */ /* MIF Big-Band Output Enable. THis 1-bit register is used to enable * ('1') or disable ('0') the I-directional driver on the MII when the * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled * when data bits are transferred from the MIF to the transceiver, and it * should be disabled when the interface is idle or when data bits are * transferred from the transceiver to the MIF (data portion of a read * instruction). Only one MDIO will be enabled at a given time, depending * on the state of the PHY_Select bit in the MIF Configuration Register. */ /* MIF Configuration Register. This 15-bit register controls the operation * of the MIF. */ #define MIF_CFG_PSELECT … #define MIF_CFG_POLL … #define MIF_CFG_BBMODE … #define MIF_CFG_PRADDR … #define MIF_CFG_MDI0 … #define MIF_CFG_MDI1 … #define MIF_CFG_PPADDR … /* MIF Frame/Output Register. This 32-bit register allows the host to * communicate with a transceiver in frame mode (as opposed to big-bang * mode). Writes by the host specify an instrution. After being issued * the host must poll this register for completion. Also, after * completion this register holds the data returned by the transceiver * if applicable. */ #define MIF_FRAME_ST … #define MIF_FRAME_OP … #define MIF_FRAME_PHYAD … #define MIF_FRAME_REGAD … #define MIF_FRAME_TAMSB … #define MIF_FRAME_TALSB … #define MIF_FRAME_DATA … /* MIF Status Register. This register reports status when the MIF is * operating in the poll mode. The poll status field is auto-clearing * on read. */ #define MIF_STATUS_DATA … #define MIF_STATUS_STAT … /* MIF Mask Register. This 16-bit register is used when in poll mode * to say which bits of the polled register will cause an interrupt * when changed. */ /* PCS/Serialink Registers */ #define PCS_MIICTRL … #define PCS_MIISTAT … #define PCS_MIIADV … #define PCS_MIILP … #define PCS_CFG … #define PCS_SMACHINE … #define PCS_ISTAT … #define PCS_DMODE … #define PCS_SCTRL … #define PCS_SOS … #define PCS_SSTATE … /* PCD MII Control Register. */ #define PCS_MIICTRL_SPD … #define PCS_MIICTRL_CT … #define PCS_MIICTRL_DM … #define PCS_MIICTRL_RAN … #define PCS_MIICTRL_ISO … #define PCS_MIICTRL_PD … #define PCS_MIICTRL_ANE … #define PCS_MIICTRL_SS … #define PCS_MIICTRL_WB … #define PCS_MIICTRL_RST … /* PCS MII Status Register. */ #define PCS_MIISTAT_EC … #define PCS_MIISTAT_JD … #define PCS_MIISTAT_LS … #define PCS_MIISTAT_ANA … #define PCS_MIISTAT_RF … #define PCS_MIISTAT_ANC … #define PCS_MIISTAT_ES … /* PCS MII Advertisement Register. */ #define PCS_MIIADV_FD … #define PCS_MIIADV_HD … #define PCS_MIIADV_SP … #define PCS_MIIADV_AP … #define PCS_MIIADV_RF … #define PCS_MIIADV_ACK … #define PCS_MIIADV_NP … /* PCS MII Link Partner Ability Register. This register is equivalent * to the Link Partnet Ability Register of the standard MII register set. * It's layout corresponds to the PCS MII Advertisement Register. */ /* PCS Configuration Register. */ #define PCS_CFG_ENABLE … #define PCS_CFG_SDO … #define PCS_CFG_SDL … #define PCS_CFG_JS … #define PCS_CFG_TO … /* PCS Interrupt Status Register. This register is self-clearing * when read. */ #define PCS_ISTAT_LSC … /* Datapath Mode Register. */ #define PCS_DMODE_SM … #define PCS_DMODE_ESM … #define PCS_DMODE_MGM … #define PCS_DMODE_GMOE … /* Serialink Control Register. * * NOTE: When in SERDES mode, the loopback bit has inverse logic. */ #define PCS_SCTRL_LOOP … #define PCS_SCTRL_ESCD … #define PCS_SCTRL_LOCK … #define PCS_SCTRL_EMP … #define PCS_SCTRL_STEST … #define PCS_SCTRL_PDWN … #define PCS_SCTRL_RXZ … #define PCS_SCTRL_RXP … #define PCS_SCTRL_TXZ … #define PCS_SCTRL_TXP … /* Shared Output Select Register. For test and debug, allows multiplexing * test outputs into the PROM address pins. Set to zero for normal * operation. */ #define PCS_SOS_PADDR … /* PROM Image Space */ #define PROM_START … #define PROM_SIZE … #define PROM_END … /* MII definitions missing from mii.h */ #define BMCR_SPD2 … #define LPA_PAUSE … /* More PHY registers (specific to Broadcom models) */ /* MII BCM5201 MULTIPHY interrupt register */ #define MII_BCM5201_INTERRUPT … #define MII_BCM5201_INTERRUPT_INTENABLE … #define MII_BCM5201_AUXMODE2 … #define MII_BCM5201_AUXMODE2_LOWPOWER … #define MII_BCM5201_MULTIPHY … /* MII BCM5201 MULTIPHY register bits */ #define MII_BCM5201_MULTIPHY_SERIALMODE … #define MII_BCM5201_MULTIPHY_SUPERISOLATE … /* MII BCM5400 1000-BASET Control register */ #define MII_BCM5400_GB_CONTROL … #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP … /* MII BCM5400 AUXCONTROL register */ #define MII_BCM5400_AUXCONTROL … #define MII_BCM5400_AUXCONTROL_PWR10BASET … /* MII BCM5400 AUXSTATUS register */ #define MII_BCM5400_AUXSTATUS … #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK … #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT … /* When it can, GEM internally caches 4 aligned TX descriptors * at a time, so that it can use full cacheline DMA reads. * * Note that unlike HME, there is no ownership bit in the descriptor * control word. The same functionality is obtained via the TX-Kick * and TX-Complete registers. As a result, GEM need not write back * updated values to the TX descriptor ring, it only performs reads. * * Since TX descriptors are never modified by GEM, the driver can * use the buffer DMA address as a place to keep track of allocated * DMA mappings for a transmitted packet. */ struct gem_txd { … }; #define TXDCTRL_BUFSZ … #define TXDCTRL_CSTART … #define TXDCTRL_COFF … #define TXDCTRL_CENAB … #define TXDCTRL_EOF … #define TXDCTRL_SOF … #define TXDCTRL_INTME … #define TXDCTRL_NOCRC … /* GEM requires that RX descriptors are provided four at a time, * aligned. Also, the RX ring may not wrap around. This means that * there will be at least 4 unused descriptor entries in the middle * of the RX ring at all times. * * Similar to HME, GEM assumes that it can write garbage bytes before * the beginning of the buffer and right after the end in order to DMA * whole cachelines. * * Unlike for TX, GEM does update the status word in the RX descriptors * when packets arrive. Therefore an ownership bit does exist in the * RX descriptors. It is advisory, GEM clears it but does not check * it in any way. So when buffers are posted to the RX ring (via the * RX Kick register) by the driver it must make sure the buffers are * truly ready and that the ownership bits are set properly. * * Even though GEM modifies the RX descriptors, it guarantees that the * buffer DMA address field will stay the same when it performs these * updates. Therefore it can be used to keep track of DMA mappings * by the host driver just as in the TX descriptor case above. */ struct gem_rxd { … }; #define RXDCTRL_TCPCSUM … #define RXDCTRL_BUFSZ … #define RXDCTRL_OWN … #define RXDCTRL_HASHVAL … #define RXDCTRL_HPASS … #define RXDCTRL_ALTMAC … #define RXDCTRL_BAD … #define RXDCTRL_FRESH(gp) … #define TX_RING_SIZE … #define RX_RING_SIZE … #if TX_RING_SIZE == 32 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 64 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 128 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 256 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 512 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 1024 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 2048 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 4096 #define TXDMA_CFG_BASE … #elif TX_RING_SIZE == 8192 #define TXDMA_CFG_BASE … #else #error TX_RING_SIZE value is illegal... #endif #if RX_RING_SIZE == 32 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 64 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 128 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 256 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 512 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 1024 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 2048 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 4096 #define RXDMA_CFG_BASE … #elif RX_RING_SIZE == 8192 #define RXDMA_CFG_BASE … #else #error RX_RING_SIZE is illegal... #endif #define NEXT_TX(N) … #define NEXT_RX(N) … #define TX_BUFFS_AVAIL(GP) … #define RX_OFFSET … #define RX_BUF_ALLOC_SIZE(gp) … #define RX_COPY_THRESHOLD … #if TX_RING_SIZE < 128 #define INIT_BLOCK_TX_RING_SIZE … #else #define INIT_BLOCK_TX_RING_SIZE … #endif #if RX_RING_SIZE < 128 #define INIT_BLOCK_RX_RING_SIZE … #else #define INIT_BLOCK_RX_RING_SIZE … #endif struct gem_init_block { … }; enum gem_phy_type { … }; enum link_state { … }; struct gem { … }; #define found_mii_phy(gp) … #endif /* _SUNGEM_H */
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