/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2020, Intel Corporation * DWMAC Intel header file */ #ifndef __DWMAC_INTEL_H__ #define __DWMAC_INTEL_H__ #define POLL_DELAY_US … /* SERDES Register */ #define SERDES_GCR … #define SERDES_GSR0 … #define SERDES_GCR0 … /* SERDES defines */ #define SERDES_PLL_CLK … #define SERDES_PHY_RX_CLK … #define SERDES_RST … #define SERDES_PWR_ST_MASK … #define SERDES_RATE_MASK … #define SERDES_PCLK_MASK … #define SERDES_LINK_MODE_MASK … #define SERDES_LINK_MODE_SHIFT … #define SERDES_PWR_ST_SHIFT … #define SERDES_PWR_ST_P0 … #define SERDES_PWR_ST_P3 … #define SERDES_LINK_MODE_2G5 … #define SERSED_LINK_MODE_1G … #define SERDES_PCLK_37p5MHZ … #define SERDES_PCLK_70MHZ … #define SERDES_RATE_PCIE_GEN1 … #define SERDES_RATE_PCIE_GEN2 … #define SERDES_RATE_PCIE_SHIFT … #define SERDES_PCLK_SHIFT … #define INTEL_MGBE_ADHOC_ADDR … #define INTEL_MGBE_XPCS_ADDR … /* Cross-timestamping defines */ #define ART_CPUID_LEAF … #define EHL_PSE_ART_MHZ … /* Selection for PTP Clock Freq belongs to PSE & PCH GbE */ #define PSE_PTP_CLK_FREQ_MASK … #define PSE_PTP_CLK_FREQ_19_2MHZ … #define PSE_PTP_CLK_FREQ_200MHZ … #define PSE_PTP_CLK_FREQ_256MHZ … #define PCH_PTP_CLK_FREQ_MASK … #define PCH_PTP_CLK_FREQ_19_2MHZ … #define PCH_PTP_CLK_FREQ_200MHZ … #endif /* __DWMAC_INTEL_H__ */
Codebase Browser
linux