// SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2020, Intel Corporation */ #include <linux/clk-provider.h> #include <linux/pci.h> #include <linux/dmi.h> #include "dwmac-intel.h" #include "dwmac4.h" #include "stmmac.h" #include "stmmac_ptp.h" struct intel_priv_data { … }; /* This struct is used to associate PCI Function of MAC controller on a board, * discovered via DMI, with the address of PHY connected to the MAC. The * negative value of the address means that MAC controller is not connected * with PHY. */ struct stmmac_pci_func_data { … }; struct stmmac_pci_dmi_data { … }; struct stmmac_pci_info { … }; static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, const struct dmi_system_id *dmi_list) { … } static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, int phyreg, u32 mask, u32 val) { … } static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) { … } static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) { … } static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) { … } /* Program PTP Clock Frequency for different variant of * Intel mGBE that has slightly different GPO mapping */ static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv) { … } static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr, u64 *art_time) { … } static int stmmac_cross_ts_isr(struct stmmac_priv *priv) { … } static int intel_crosststamp(ktime_t *device, struct system_counterval_t *system, void *ctx) { … } static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv, int base) { … } static void common_default_data(struct plat_stmmacenet_data *plat) { … } static struct phylink_pcs *intel_mgbe_select_pcs(struct stmmac_priv *priv, phy_interface_t interface) { … } static int intel_mgbe_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static int ehl_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static int ehl_sgmii_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_sgmii1g_info = …; static int ehl_rgmii_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_rgmii1g_info = …; static int ehl_pse0_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_pse0_rgmii1g_info = …; static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_pse0_sgmii1g_info = …; static int ehl_pse1_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_pse1_rgmii1g_info = …; static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info ehl_pse1_sgmii1g_info = …; static int tgl_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static int tgl_sgmii_phy0_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info tgl_sgmii1g_phy0_info = …; static int tgl_sgmii_phy1_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info tgl_sgmii1g_phy1_info = …; static int adls_sgmii_phy0_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info adls_sgmii1g_phy0_info = …; static int adls_sgmii_phy1_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static struct stmmac_pci_info adls_sgmii1g_phy1_info = …; static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = …; static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = …; static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = …; static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = …; static const struct dmi_system_id quark_pci_dmi[] = …; static int quark_default_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { … } static const struct stmmac_pci_info quark_info = …; static int stmmac_config_single_msi(struct pci_dev *pdev, struct plat_stmmacenet_data *plat, struct stmmac_resources *res) { … } static int stmmac_config_multi_msi(struct pci_dev *pdev, struct plat_stmmacenet_data *plat, struct stmmac_resources *res) { … } /** * intel_eth_pci_probe * * @pdev: pci device pointer * @id: pointer to table of device id/id's. * * Description: This probing function gets called for all PCI devices which * match the ID table and are not "owned" by other driver yet. This function * gets passed a "struct pci_dev *" for each device whose entry in the ID table * matches the device. The probe functions returns zero when the driver choose * to take "ownership" of the device or an error code(-ve no) otherwise. */ static int intel_eth_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } /** * intel_eth_pci_remove * * @pdev: pci device pointer * Description: this function calls the main to free the net resources * and releases the PCI resources. */ static void intel_eth_pci_remove(struct pci_dev *pdev) { … } static int __maybe_unused intel_eth_pci_suspend(struct device *dev) { … } static int __maybe_unused intel_eth_pci_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, intel_eth_pci_resume); #define PCI_DEVICE_ID_INTEL_QUARK … #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 … /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC * which are named PSE0 and PSE1 */ #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 … #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G … #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 … #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 … #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 … #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G … #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 … #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 … #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G … #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G … static const struct pci_device_id intel_eth_pci_id_table[] = …; MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); static struct pci_driver intel_eth_pci_driver = …; module_pci_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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